####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := ad_ip_jesd204_tpl_adc

GENERIC_DEPS += ../../common/ad_datafmt.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_pnmon.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/ad_xcvr_rx_if.v
GENERIC_DEPS += ../../common/up_adc_channel.v
GENERIC_DEPS += ../../common/up_adc_common.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v
GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v

XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl

INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ../../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
INTEL_DEPS += ad_ip_jesd204_tpl_adc_hw.tcl

include ../../scripts/library.mk