`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/27 15:30:06
// Design Name: 
// Module Name: glink_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module glink_top(
    // glink gt reference clock
    input           glink_refclk_p      , // generated by oscillator, 125mhz
    input           glink_refclk_n      ,
    // glink pk clock
    input           glink_logic_clk      , // generated by oscillator, 25mhz

    input           pl_rst              ,

    input           rx_datain_p_ch_a    ,
	input           rx_datain_n_ch_a    ,
	input           rx_datain_p_ch_b    ,
	input           rx_datain_n_ch_b    ,
	
	output          tx_dataout_p_ch_a   ,
	output 	        tx_dataout_n_ch_a   ,
	output 	        tx_dataout_p_ch_b   ,
	output 	        tx_dataout_n_ch_b   ,

    //glink_ctrl
    output  [31:0]  glink_gpio_i_0      ,
    output  [31:0]  glink_gpio_i_1      ,
    input   [31:0]  glink_gpio_o_0      ,
    input   [31:0]  glink_gpio_o_1      ,

    //DMA_send_fifo
    input   [15:0]  glink_tx_fifo_tdata ,
    input           glink_tx_fifo_tlast ,
    output          glink_tx_fifo_tready,
    input           glink_tx_fifo_tvalid,

    //DMA_recv_fifo
    output  [15:0]  glink_rx_fifo_tdata ,
    output          glink_rx_fifo_tlast ,
    input           glink_rx_fifo_tready,
    output          glink_rx_fifo_tvalid, 

    output          glink_ip_clk
    );

wire glink_pll_inclk;
IBUFDS_GTE2 IBUFDS_GTE2_CLK1(
    .I      (glink_refclk_p ),
    .IB     (glink_refclk_n ),
    .CEB    (1'b0           ),
    .O      (glink_pll_inclk),
    .ODIV2  (               )
);

wire glink_rst;
glink_rst_create u_glink_rst_create(
    .glink_logic_clk(glink_logic_clk    ),
    .i_reset_p      (pl_rst             ),
    .reset_p        (glink_rst          )
);

wire [11:0] i_node_id           ;
wire        i_node_id_par       ;
wire [15:0] i_smartnc_2nd_cfg   ;
wire [15:0] i_smartnc_3rd_cfg   ;
wire [15:0] i_smartnt_cfg       ;
    
wire        smartnc_trans_trig          ;
wire        smartnc_trans_reset         ;
wire        smartnc_trans_idle          ;
wire        smartnc_trans_err           ;
wire [15:0] smartnc_intf_tx_fifo_wdata  ;
wire        smartnc_intf_tx_fifo_wr_en  ;
wire        smartnc_intf_tx_fifo_afull  ;
wire        smartnc_intf_rx_fifo_empty  ;
wire [15:0] smartnc_intf_rx_fifo_rdata  ;
wire        smartnc_intf_rx_fifo_rd_en  ;
    
wire        smartnt_intf_cmd_proc_req   ;
wire        smartnt_intf_cmd_proc_ack   ;
wire        smartnt_intf_rx_fifo_empty  ;
wire [15:0] smartnt_intf_rx_fifo_rdata  ;
wire        smartnt_intf_rx_fifo_rd_en  ;
wire [15:0] smartnt_intf_tx_fifo_wdata  ;
wire        smartnt_intf_tx_fifo_wr_en  ;
    
wire        glink_ip_rst_n              ;

ebey_glink_top_wrapper_k7_smartncnt u_ebey_glink_top_wrapper_k7_smartncnt
(   .clk_reconfig               (glink_logic_clk            ),
    .pll_inclk                  (glink_pll_inclk            ),
    .i_reset_p                  (glink_rst                  ),

    .i_node_id                  (i_node_id                  ),//�ڵ� ID12'h003
    .i_node_id_par              (i_node_id_par              ),//��żУ�� 1'b1 
    .i_smartnc_2nd_cfg          (i_smartnc_2nd_cfg          ),//SMARTNC���䳬ʱΪ128us 16'h0003 
    .i_smartnc_3rd_cfg          (i_smartnc_3rd_cfg          ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
    .i_smartnt_cfg              (i_smartnt_cfg              ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000

	.i_select_n                 (1'b1                       ),
    .i_strbd_n                  (1'b1                       ),
    .i_mem_access               (1'b0                       ),
    .i_rd_access                (1'b0                       ),
    .o_ready_n                  (                           ),
    .i_cpu_addr                 (18'b0                      ),
    .o_cpu_rdata                (                           ),
    .o_cpu_rdata_oe             (                           ),
    .i_cpu_wdata                (16'b0                      ),
	 
    .smartnc_trans_trig         (smartnc_trans_trig         ),
    .smartnc_trans_reset        (smartnc_trans_reset        ),
    .smartnc_trans_idle         (smartnc_trans_idle         ),
    .smartnc_trans_err          (smartnc_trans_err          ),
    .smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
    .smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
    .smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
    .smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
    .smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
    .smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),
    
    .smartnt_intf_cmd_proc_req  (smartnt_intf_cmd_proc_req  ),
    .smartnt_intf_cmd_proc_ack  (smartnt_intf_cmd_proc_ack  ),
    .smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
    .smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
    .smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
    .smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
    .smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),
    
    .rx_datain_p_ch_a           (rx_datain_p_ch_a           ),
    .rx_datain_n_ch_a           (rx_datain_n_ch_a           ),
    .rx_datain_p_ch_b           (rx_datain_p_ch_b           ),
    .rx_datain_n_ch_b           (rx_datain_n_ch_b           ),
    .tx_dataout_p_ch_a          (tx_dataout_p_ch_a          ),
    .tx_dataout_n_ch_a          (tx_dataout_n_ch_a          ),
    .tx_dataout_p_ch_b          (tx_dataout_p_ch_b          ),
    .tx_dataout_n_ch_b          (tx_dataout_n_ch_b          ),

    .clk_ip                     (glink_ip_clk               ),
    .o_reset_n                  (glink_ip_rst_n             )
);


 glink_smartncnt_intf u_glink_smartncnt_intf(
    .clk                        (glink_ip_clk               ),
    .rst_n                      (glink_ip_rst_n             ),

    .glink_gpio_i_0             (glink_gpio_i_0             ), // PS <- Glink
    .glink_gpio_i_1             (glink_gpio_i_1             ), // PS <- Glink
    .glink_gpio_o_0             (glink_gpio_o_0             ), // PS -> Glink
    .glink_gpio_o_1             (glink_gpio_o_1             ), // PS -> Glink

    .i_node_id                  (i_node_id                  ),//�ڵ� ID12'h003
    .i_node_id_par              (i_node_id_par              ),//��żУ�� 1'b1 
    .i_smartnc_2nd_cfg          (i_smartnc_2nd_cfg          ),//SMARTNC���䳬ʱΪ128us 16'h0003 
    .i_smartnc_3rd_cfg          (i_smartnc_3rd_cfg          ),//����Ϊ�̱��Ĺ���ģʽ 16'h0400
    .i_smartnt_cfg              (i_smartnt_cfg              ),//����Ϊ�̱��Ĺ���ģʽ 16'h4000

    .smartnc_trans_trig         (smartnc_trans_trig         ),//gpio control
    .smartnc_trans_reset        (smartnc_trans_reset        ),//gpio control
    .smartnc_trans_idle         (smartnc_trans_idle         ),
    .smartnc_trans_err          (smartnc_trans_err          ),//gpio control
    .smartnc_intf_tx_fifo_wdata (smartnc_intf_tx_fifo_wdata ),
    .smartnc_intf_tx_fifo_wr_en (smartnc_intf_tx_fifo_wr_en ),
    .smartnc_intf_tx_fifo_afull (smartnc_intf_tx_fifo_afull ),
    .smartnc_intf_rx_fifo_empty (smartnc_intf_rx_fifo_empty ),
    .smartnc_intf_rx_fifo_rdata (smartnc_intf_rx_fifo_rdata ),
    .smartnc_intf_rx_fifo_rd_en (smartnc_intf_rx_fifo_rd_en ),

    .smartnt_intf_cmd_proc_req  (smartnt_intf_cmd_proc_req  ),
    .smartnt_intf_cmd_proc_ack  (smartnt_intf_cmd_proc_ack  ),
    .smartnt_intf_rx_fifo_empty (smartnt_intf_rx_fifo_empty ),
    .smartnt_intf_rx_fifo_rdata (smartnt_intf_rx_fifo_rdata ),
    .smartnt_intf_rx_fifo_rd_en (smartnt_intf_rx_fifo_rd_en ),
    .smartnt_intf_tx_fifo_wdata (smartnt_intf_tx_fifo_wdata ),
    .smartnt_intf_tx_fifo_wr_en (smartnt_intf_tx_fifo_wr_en ),

    .glink_tx_fifo_tdata        (glink_tx_fifo_tdata[15:0]  ),
    .glink_tx_fifo_tlast        (glink_tx_fifo_tlast        ),
    .glink_tx_fifo_tready       (glink_tx_fifo_tready       ),
    .glink_tx_fifo_tvalid       (glink_tx_fifo_tvalid       ),

    .glink_rx_fifo_tdata        (glink_rx_fifo_tdata[15:0]  ),
    .glink_rx_fifo_tlast        (glink_rx_fifo_tlast        ),
    .glink_rx_fifo_tready       (glink_rx_fifo_tready       ),
    .glink_rx_fifo_tvalid       (glink_rx_fifo_tvalid       )
);

endmodule