analog.com user util_upack2 1.0 s_axis TREADY s_axis_ready TVALID s_axis_valid TDATA s_axis_data s_axis_signal_clock s_axis_signal_clock CLK clk ASSOCIATED_BUSIF s_axis ASSOCIATED_RESET reset s_axis_signal_reset s_axis_signal_reset RST reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_upack2 xilinx_anylanguagesynthesis_view_fileset viewChecksum 7dfed517 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_upack2 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 7dfed517 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 31df22aa clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_8 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_9 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_10 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_11 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_12 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_13 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_14 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_16 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_17 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_18 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_19 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_20 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_21 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_22 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_23 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_24 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_25 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_26 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_27 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_28 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_29 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_30 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_31 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_32 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_33 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_34 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_35 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_36 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_37 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_38 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_39 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_40 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_41 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_42 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_43 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_44 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_45 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_46 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_47 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_48 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_49 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_50 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_51 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_52 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_53 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_54 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_55 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_56 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_57 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_58 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_59 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_60 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_61 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_62 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_63 in std_logic xilinx_anylanguagesynthesis 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std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_58 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_59 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_60 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_61 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_62 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_rd_data_63 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 NUM_OF_CHANNELS Num Of Channels 4 SAMPLES_PER_CHANNEL Samples Per Channel 1 SAMPLE_DATA_WIDTH Sample Data Width 16 xilinx_anylanguagesynthesis_view_fileset ../../common/ad_perfect_shuffle.v verilogSource ../util_pack_common/pack_ctrl.v verilogSource ../util_pack_common/pack_interconnect.v verilogSource ../util_pack_common/pack_network.v verilogSource ../util_pack_common/pack_shell.v verilogSource util_upack2_impl.v verilogSource util_upack2.v verilogSource CHECKSUM_0a9a4b8f xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_perfect_shuffle.v verilogSource ../util_pack_common/pack_ctrl.v verilogSource ../util_pack_common/pack_interconnect.v verilogSource ../util_pack_common/pack_network.v verilogSource ../util_pack_common/pack_shell.v verilogSource util_upack2_impl.v verilogSource util_upack2.v verilogSource xilinx_xpgui_view_fileset xgui/util_upack2_v1_0.tcl tclSource CHECKSUM_31df22aa XGUI_VERSION_2 util_upack2_v1_0 NUM_OF_CHANNELS Number of Channels 4 SAMPLES_PER_CHANNEL Samples per Channel 1 SAMPLE_DATA_WIDTH Sample Width 16 Component_Name util_upack2_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_upack2_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:24:05Z 2019.1.3