analog.com user axi_i2s_adi 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW m_axis TDATA m_axis_tdata TKEEP m_axis_tkeep TLAST m_axis_tlast TVALID m_axis_tvalid TREADY m_axis_tready true s_axis TDATA s_axis_tdata TLAST s_axis_tlast TVALID s_axis_tvalid TREADY s_axis_tready true dma_req_rx_aclk CLK dma_req_rx_aclk ASSOCIATED_RESET dma_req_rx_rstn dma_req_tx_aclk CLK dma_req_tx_aclk ASSOCIATED_RESET dma_req_tx_rstn m_axis_aclk CLK m_axis_aclk ASSOCIATED_BUSIF m_axis s_axis_aclk CLK s_axis_aclk ASSOCIATED_BUSIF s_axis ASSOCIATED_RESET s_axis_aresetn dma_req_rx_rstn RST dma_req_rx_rstn POLARITY ACTIVE_LOW dma_req_tx_rstn RST dma_req_tx_rstn POLARITY ACTIVE_LOW s_axis_aresetn RST s_axis_aresetn POLARITY ACTIVE_LOW dma_ack_rx TVALID dma_req_rx_davalid TREADY dma_req_rx_daready TUSER dma_req_rx_datype false dma_req_rx TVALID dma_req_rx_drvalid TREADY dma_req_rx_drready TUSER dma_req_rx_drtype TLAST dma_req_rx_drlast false dma_req_rx_dma_ack_rx_signal_clock dma_req_rx_dma_ack_rx_signal_clock CLK dma_req_rx_aclk ASSOCIATED_BUSIF dma_req_rx:dma_ack_rx ASSOCIATED_RESET dma_req_rx_rstn dma_req_rx_dma_ack_rx_signal_reset dma_req_rx_dma_ack_rx_signal_reset RST dma_req_rx_rstn POLARITY ACTIVE_LOW dma_ack_tx TVALID dma_req_tx_davalid TREADY dma_req_tx_daready TUSER dma_req_tx_datype false dma_req_tx TVALID dma_req_tx_drvalid TREADY dma_req_tx_drready TUSER dma_req_tx_drtype TLAST dma_req_tx_drlast false dma_req_tx_dma_ack_tx_signal_clock dma_req_tx_dma_ack_tx_signal_clock CLK dma_req_tx_aclk ASSOCIATED_BUSIF dma_req_tx:dma_ack_tx ASSOCIATED_RESET dma_req_tx_rstn dma_req_tx_dma_ack_tx_signal_reset dma_req_tx_dma_ack_tx_signal_reset RST dma_req_tx_rstn POLARITY ACTIVE_LOW i2s BCLK bclk_o LRCLK lrclk_o SDATA_OUT sdata_o SDATA_IN sdata_i i2s_signal_clock i2s_signal_clock CLK data_clk_i ASSOCIATED_BUSIF i2s s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_i2s_adi xilinx_anylanguagesynthesis_view_fileset viewChecksum c98c1820 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_i2s_adi xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 5a13822f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 4823b664 data_clk_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bclk_o out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation lrclk_o out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdata_o out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdata_i in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true m_axis_tkeep out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true dma_req_tx_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_davalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_datype in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_daready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_drvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_drtype out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_drlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_tx_drready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_davalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_datype in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_daready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_drvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_drtype out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_drlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false dma_req_rx_drready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awaddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 SLOT_WIDTH Slot Width 24 LRCLK_POL Lrclk Pol 0 BCLK_POL Bclk Pol 0 S_AXI_DATA_WIDTH S Axi Data Width 32 S_AXI_ADDRESS_WIDTH S Axi Address Width 32 DEVICE_FAMILY Device Family virtex6 DMA_TYPE Dma Type 0 NUM_OF_CHANNEL Num Of Channel 1 HAS_TX Has Tx 1 HAS_RX Has Rx 1 choice_list_388a2eb3 16 20 24 32 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_2af915b7 0 1 choice_pairs_c9229ef9 0 1 xilinx_anylanguagesynthesis_view_fileset axi_i2s_adi_constr.xdc xdc processing_order late ../common/axi_ctrlif.vhd vhdlSource fifo_synchronizer.vhd vhdlSource i2s_clkgen.vhd vhdlSource i2s_tx.vhd vhdlSource i2s_rx.vhd vhdlSource i2s_controller.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_rx_fifo.vhd vhdlSource ../common/axi_streaming_dma_tx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource axi_i2s_adi.vhd vhdlSource CHECKSUM_e6503276 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/axi_ctrlif.vhd vhdlSource fifo_synchronizer.vhd vhdlSource i2s_clkgen.vhd vhdlSource i2s_tx.vhd vhdlSource i2s_rx.vhd vhdlSource i2s_controller.vhd vhdlSource ../common/dma_fifo.vhd vhdlSource ../common/axi_streaming_dma_rx_fifo.vhd vhdlSource ../common/axi_streaming_dma_tx_fifo.vhd vhdlSource ../common/pl330_dma_fifo.vhd vhdlSource axi_i2s_adi.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axi_i2s_adi_v1_0.tcl tclSource CHECKSUM_aab16c86 XGUI_VERSION_2 ADI AXI I2S Controller SLOT_WIDTH Slot Width 24 LRCLK_POL Left-Right Clock Polarity 0 BCLK_POL Bit Clock Polarity 0 S_AXI_DATA_WIDTH S Axi Data Width 32 S_AXI_ADDRESS_WIDTH AXI Address Width 32 DEVICE_FAMILY Device Family virtex6 DMA_TYPE DMA Interface Type 0 NUM_OF_CHANNEL Number of Audio Channels 1 HAS_TX Enable I2S Transmitter Support 1 HAS_RX Enable I2S Receiver Support 1 Component_Name axi_i2s_adi_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices ADI AXI I2S Controller package_project Analog Devices http://www.analog.com 1 2021-12-09T07:15:23Z 2019.1.3