`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // _ _ ____ // | | ___ ___| |__ / ___| __ _ ___ // _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ // | |_| | (_) \__ \ | | | | |_| | (_| | (_) | // \___/ \___/|___/_| |_| \____|\__,_|\___/ // // Create Date: 2021/12/14 15:54:11 // Design Name: // Module Name: system_top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module system_top ( /*************************************************************************** * Contents * 01. Clocks * 02. AD9516 Interface * 03. AD9361-1 Interface * 04. AD9361-2 Interface * 05. Phased-Array Control * 06. RF Synthesizer Control * 07. LVDS for Time Synchronization * 08. Debug IO **************************************************************************/ // ************************************************************************* // ******************************** Clocks ********************************* // ************************************************************************* // power-up configure clock input clk_25m , // 250mhz backup clock input clk_250m_p , // generated by ad9516, 250mhz input clk_250m_n , // ad9361 buffered clock input ad9361_1_buffer_clk , // derived from ad9361 input clock input ad9361_2_buffer_clk , // derived from ad9361 input clock // ************************************************************************* // *************************** AD9516 Interface **************************** // ************************************************************************* // spi interface output ad9516_spi_clk , output ad9516_spi_csn , inout ad9516_spi_mosi , input ad9516_spi_miso , // control signals input ad9516_refmon , // ad9516 reference clock monitor input ad9516_ld , // ad9516 lock detect input ad9516_status , // ad9516 multiple selectable status output output ad9516_pd_b , // ad9516 active-low power down control output ad9516_reset_b , // ad9516 active-low reset control output ad9516_sync_b , // ad9516 active-low manual synchronization control // ************************************************************************* // ************************** AD9361-1 Interface *************************** // ************************************************************************* // rx data (rx channels are tied to ground physically) input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz input ad9361_1_rx_frame , input [11:0] ad9361_1_rx_data , // tx data output ad9361_1_tx_fb_clk , output ad9361_1_tx_frame , output [11:0] ad9361_1_tx_data , // spi interface output ad9361_1_spi_clk , output ad9361_1_spi_csn , inout ad9361_1_spi_mosi , input ad9361_1_spi_miso , // control signals output ad9361_1_reset_b , // ad9361 active-low reset control output ad9361_1_en_agc , // ad9361 manual agc control output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed) output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) output [ 3:0] ad9361_1_ctrl_in , input [ 7:0] ad9361_1_ctrl_out , output ad9361_sync , // ************************************************************************* // ************************** AD9361-2 Interface *************************** // ************************************************************************* // rx data (rx channels are tied to ground physically) input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz input ad9361_2_rx_frame , input [11:0] ad9361_2_rx_data , // tx data output ad9361_2_tx_fb_clk , output ad9361_2_tx_frame , output [11:0] ad9361_2_tx_data , // spi interface output ad9361_2_spi_clk , output ad9361_2_spi_csn , inout ad9361_2_spi_mosi , input ad9361_2_spi_miso , // control signals output ad9361_2_reset_b , // ad9361 active-low reset control output ad9361_2_en_agc , // ad9361 manual agc control output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed) output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) output [ 3:0] ad9361_2_ctrl_in , input [ 7:0] ad9361_2_ctrl_out , // ************************************************************************* // ************************* Phased-Array Control ************************** // ************************************************************************* output ant_cin , output ant_din0 , output ant_din1 , input ant_cout , input ant_dout0 , input ant_dout1 , output ant_tr , output ant_dary , // ************************************************************************* // ************************ RF Synthesizer Control ************************* // ************************************************************************* output rf_standby , output rf_sw_pll , output rf_t , output rf_r , output rf_sw_bpf , output rf_sclk1 , output rf_sdio1 , output rf_cs1 , input rf_ld1 , output rf_sclk2 , output rf_sdio2 , output rf_cs2 , input rf_ld2 , output rf_sclk3 , output rf_sdio3 , output rf_cs3 , input rf_ld3 , output rf_tmgc_16 , output rf_tmgc_8 , output rf_tmgc_4 , output rf_tmgc_2 , output rf_tmgc_1 , output rf_rmgc_16 , output rf_rmgc_8 , output rf_rmgc_4 , output rf_rmgc_2 , output rf_rmgc_1 , output rf_enable , output rf_sc , output rf_sd , output rf_endsyn , input rf_sdout , inout rf_dq_wd , output rf_sw_rx , // ************************************************************************* // ********************* LVDS for Time Synchronization ********************* // ************************************************************************* // 1st group input lvds_in_1 , output lvds_out_1 , // 2nd group (these pins can be disconnected physically) input lvds_in_2 , output lvds_out_2 , // ************************************************************************* // ******************************* Debug IO ******************************** // ************************************************************************* // 3.3v ports output uart1_txd , input uart1_rxd , output uart2_txd , input uart2_rxd , output uart3_txd , input uart3_rxd , inout debug_io_1 , inout debug_io_2 , inout debug_io_3 , inout debug_io_4 , inout debug_io_5 , inout debug_io_6 , inout debug_io_7 , inout debug_io_8 , // 1.8v ports inout debug_io_00_p , inout debug_io_01_p , inout debug_io_02_p , inout debug_io_03_p , inout debug_io_04_p , inout debug_io_05_p , inout debug_io_06_p , inout debug_io_07_p , inout debug_io_08_p ); /******************************************************************************* * Contents * 01. Input/Output Buffer * 02. System Clock Generation * 03. Block Design Interface * 04. Phased-Array Control * 05. RF Synthesizer Control * 06. LVDS for Time Synchronization * 07. Tx Signals * 08. Rx Signals * 09. ILAs and VIOs ******************************************************************************/ //////////////////////////////////////////////////////////////////////////////// /////////////////////////// System Clock Generation //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // global reset wire sys_rst ; // global reset signal, active high wire ant_rst ; // phased-array & rf control reset signal, active high // pl signal processing clock wire sys_clk ; // 48MHz 41.6667MHz wire sys_clk_2x ; // 96MHz 83.3333MHz wire sys_clk_3x ; // 144MHz 125MHz wire sys_clk_4x ; // 192MHz 166.6667MHz wire sys_clk_ld ; // system main clock locked indicator // ad9361-1 clocks wire ad9361_1_clk ; // 48MHz 41.6667MHz wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz wire ad9361_1_clk_3x ; // 144MHz 125MHz wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator // ad9361-2 clocks wire ad9361_2_clk ; // 48MHz 41.6667MHz wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz wire ad9361_2_clk_3x ; // 144MHz 125MHz wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator // phased-array & rf control clocks wire clk_96m ; wire clk_48m ; wire clk_32m ; wire clk_19p2m ; clk_dist u_clk_dist ( // input clocks .clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz .clk_250m_n (clk_250m_n ), .ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz .ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz // output clocks & reset // global reset .sys_rst (sys_rst ), // global reset signal, active high .ant_rst (ant_rst ), // phased-array & rf control reset signal, active high // pl signal processing clock .sys_clk (sys_clk ), // 48MHz 41.6667MHz .sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz .sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz .sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz .sys_clk_ld (sys_clk_ld ), // system main clock locked indicator // ad9361-1 clocks .ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz .ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz .ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz .ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz .ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator // ad9361-2 clocks .ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz .ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz .ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz .ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz .ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator // phased-array & rf control clocks .clk_96m (clk_96m ), .clk_48m (clk_48m ), .clk_32m (clk_32m ), .clk_19p2m (clk_19p2m ) ); //////////////////////////////////////////////////////////////////////////////// //////////////////////////// Block Design Interface //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // gpio wire [31:0] gpio_i; wire [31:0] gpio_o; wire ad9361_rx_fifo_rst; wire ad9361_1_cal_start; wire ad9361_1_cal_done; wire ad9361_2_cal_start; wire ad9361_2_cal_done; wire ad9361_cal_result; wire ad9361_recal; assign ad9516_pd_b = gpio_o[ 0]; assign ad9516_reset_b = gpio_o[ 1]; assign ad9516_sync_b = gpio_o[ 2]; assign ad9361_1_txnrx = gpio_o[ 3]; // ad9361 enable state machine control assign ad9361_1_enable = gpio_o[ 4]; // ad9361 enable state machine control assign ad9361_1_en_agc = gpio_o[ 5]; // ad9361 agc control assign ad9361_1_reset_b = gpio_o[ 6]; // ad9361 reset assign ad9361_1_ctrl_in = gpio_o[10:7]; assign ad9361_2_txnrx = gpio_o[11]; // ad9361 enable state machine control assign ad9361_2_enable = gpio_o[12]; // ad9361 enable state machine control assign ad9361_2_en_agc = gpio_o[13]; // ad9361 agc control assign ad9361_2_reset_b = gpio_o[14]; // ad9361 reset assign ad9361_2_ctrl_in = gpio_o[18:15]; assign ad9361_sync = gpio_o[19]; assign ad9361_rx_fifo_rst = gpio_o[20]; assign ad9361_1_cal_start = gpio_o[21]; assign ad9361_2_cal_start = gpio_o[22]; assign ad9361_recal = gpio_o[23]; assign ad9361_tx_switch = gpio_o[24]; assign gpio_i[ 7:0] = ad9361_1_ctrl_out; assign gpio_i[15:8] = ad9361_2_ctrl_out; assign gpio_i[16] = ad9516_refmon; assign gpio_i[17] = ad9516_ld; assign gpio_i[18] = ad9516_status; assign gpio_i[19] = ad9361_1_cal_done; assign gpio_i[20] = ad9361_2_cal_done; assign gpio_i[21] = ad9361_cal_result; // spi interface wire spi_sclk ; wire [ 2:0] spi_cs ; reg spi_sdi ; wire spi_sdo ; wire spi_sdo_t ; wire spi_three_wire; wire spi_active ; // ad9516 - three-wire spi or four-wire spi assign ad9516_spi_clk = spi_sclk; assign ad9516_spi_csn = spi_cs[0]; assign ad9516_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; // ad9361-1 - three-wire spi or four-wire spi assign ad9361_1_spi_clk = spi_sclk; assign ad9361_1_spi_csn = spi_cs[1]; assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; // ad9361-2 - three-wire spi or four-wire spi assign ad9361_2_spi_clk = spi_sclk; assign ad9361_2_spi_csn = spi_cs[2]; assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; // select sdi signal always @(*) begin if (~ad9516_spi_csn) spi_sdi = spi_three_wire ? ad9516_spi_mosi : ad9516_spi_miso; else if (~ad9361_1_spi_csn) spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso; else if (~ad9361_2_spi_csn) spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso; else spi_sdi = 1'bz; end // ps clock wire ps_clk_25M; system_bd_wrapper u_system_bd_wrapper ( // ps system clock input .clk_25MHz (clk_25m ), // input clk_25MHz .ps_clk_25M (ps_clk_25M ), // output ps_clk_25M // gpio, for control signals .gpio_i (gpio_i ), // input [31:0]gpio_i .gpio_o (gpio_o ), // output [31:0]gpio_o // spi interface .spi_sclk (spi_sclk ), // output spi_sclk .spi_cs (spi_cs ), // output [2:0]spi_cs .spi_sdi (spi_sdi ), // input [0:0]spi_sdi .spi_sdo (spi_sdo ), // output spi_sdo .spi_sdo_t (spi_sdo_t ), // output spi_sdo_t .spi_three_wire (spi_three_wire ), // output spi_three_wire .spi_active (spi_active ) // output spi_active ); //////////////////////////////////////////////////////////////////////////////// ///////////////// Phased-Array & RF Synthesizer Control & C2C ////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////// LVDS for Time Synchronization ///////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// Tx Signals ////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // baseband signal wire [11:0] tx_data_i; wire [11:0] tx_data_q; wire [11:0] tx_ch1_i; wire [11:0] tx_ch1_q; wire [11:0] tx_ch2_i; wire [11:0] tx_ch2_q; ad9361_tx_map_cmos_dual u_ad9361_tx_map ( .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst .tx_data_clk (sys_clk ), // input tx_data_clk .tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst .tx_ch1_i (tx_data_i ), // input [11:0] tx_ch1_i .tx_ch1_q (tx_data_q ), // input [11:0] tx_ch1_q .tx_ch2_i (tx_data_i ), // input [11:0] tx_ch2_i .tx_ch2_q (tx_data_q ), // input [11:0] tx_ch2_q .clk_out (ad9361_1_tx_fb_clk ), // output clk_out .tx_frame (ad9361_1_tx_frame ), // output tx_frame .tx_data (ad9361_1_tx_data ) // output [11:0] tx_data ); assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; // assign ad9361_2_tx_frame = ad9361_1_tx_frame ; // assign ad9361_2_tx_data = ad9361_1_tx_data ; // <---------------------------------------------------------------------------> // <--------------------- insert transmitter logic below ----------------------> // <---------------------------------------------------------------------------> wire [ 1:0] waveform_sel; wire sweep_on ; wire [31:0] freq_set ; wire [ 1:0] iq_sel ; wire [ 3:0] bb_rshift ; tx_qpsk #( .CLK_FREQ (48000000 ) ) u_tx_qpsk ( .clk (sys_clk ), // input clk .rst (sys_rst ), // input rst .tx_data_i (tx_data_i ), // output [11:0] tx_data_i .tx_data_q (tx_data_q ), // output [11:0] tx_data_q // debug ports .waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel .sweep_on (sweep_on ), // input sweep_on .freq_set (freq_set ), // input [31:0] freq_set .iq_sel (iq_sel ), // input [ 1:0] iq_sel .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift ); //////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// Rx Signals ////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// wire [11:0] rx_ch1_i, rx_ch1_q; wire [11:0] rx_ch2_i, rx_ch2_q; wire [11:0] rx_ch3_i, rx_ch3_q; wire [11:0] rx_ch4_i, rx_ch4_q; ad9361_rx_map_cmos_dual u_ad9361_1_rx_map ( .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst .rx_data_clk (sys_clk ), // input rx_data_clk .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst .rx_frame (ad9361_1_rx_frame ), // input rx_frame .rx_data (ad9361_1_rx_data ), // input [11:0] rx_data .rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i .rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q .rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i .rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q ); ad9361_rx_map_cmos_dual u_ad9361_2_rx_map ( .clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst .rx_data_clk (sys_clk ), // input rx_data_clk .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst .rx_frame (ad9361_2_rx_frame ), // input rx_frame .rx_data (ad9361_2_rx_data ), // input [11:0] rx_data .rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i .rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q .rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i .rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q ); // <---------------------------------------------------------------------------> // <----------------------- insert receiver logic below -----------------------> // <---------------------------------------------------------------------------> //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// ILAs and VIOs ///////////////////////////////// //////////////////////////////////////////////////////////////////////////////// ila_tx_rx u_ila_tx_rx ( .clk (sys_clk ), // input wire clk .probe0 (tx_ch1_i ), // input wire [11:0] probe0 .probe1 (tx_ch1_q ), // input wire [11:0] probe1 .probe2 (rx_ch1_i ), // input wire [11:0] probe2 .probe3 (rx_ch1_q ), // input wire [11:0] probe3 .probe4 (rx_ch2_i ), // input wire [11:0] probe4 .probe5 (rx_ch2_q ), // input wire [11:0] probe5 .probe6 (rx_ch3_i ), // input wire [11:0] probe6 .probe7 (rx_ch3_q ), // input wire [11:0] probe7 .probe8 (rx_ch4_i ), // input wire [11:0] probe8 .probe9 (rx_ch4_q ) // input wire [11:0] probe9 ); vio_manual_ctrl u_vio_manual_ctrl ( .clk (sys_clk ), // input wire clk .probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0 .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 ); endmodule