analog.com user util_cdc 1.0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog sync_data xilinx_anylanguagesynthesis_view_fileset viewChecksum 68b11e03 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog sync_data xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 68b11e03 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 867b5fd2 in_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation in_data in 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 out_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation out_data out 0 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_BITS Num Of Bits 1 ASYNC_CLK Async Clk 1 xilinx_anylanguagesynthesis_view_fileset sync_bits.v verilogSource sync_data.v verilogSource sync_event.v verilogSource sync_gray.v verilogSource CHECKSUM_9bb9ba26 xilinx_anylanguagebehavioralsimulation_view_fileset sync_bits.v verilogSource sync_data.v verilogSource sync_event.v verilogSource sync_gray.v verilogSource xilinx_xpgui_view_fileset xgui/sync_data_v1_0.tcl tclSource CHECKSUM_867b5fd2 XGUI_VERSION_2 ADI Clock-Domain-Crossing Utils NUM_OF_BITS Num Of Bits 1 ASYNC_CLK Async Clk 1 Component_Name sync_data_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices ADI Clock-Domain-Crossing Utils true package_project Analog Devices http://www.analog.com 1 2021-12-08T02:22:24Z 2019.1.3