Archived
33 lines
820 B
Tcl
33 lines
820 B
Tcl
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create util_axis_upscale
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adi_ip_files util_axis_upscale [list \
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"$ad_hdl_dir/library/common/util_axis_upscale.v"]
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adi_ip_properties_lite util_axis_upscale
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adi_add_bus "s_axis" "slave" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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{
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{"s_axis_valid" "TVALID"} \
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{"s_axis_ready" "TREADY"} \
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{"s_axis_data" "TDATA"} \
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}
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adi_add_bus_clock "clk" "s_axis" "resetn"
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adi_add_bus "m_axis" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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{
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{"m_axis_valid" "TVALID"} \
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{"m_axis_ready" "TREADY"} \
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{"m_axis_data" "TDATA"} \
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}
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ipx::associate_bus_interfaces -busif m_axis -clock s_axis_signal_clock [ipx::current_core]
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ipx::save_core [ipx::current_core]
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