Archived
114 lines
4.1 KiB
Verilog
114 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module pack_ctrl #(
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parameter PORT_ADDRESS_WIDTH = 2,
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parameter MUX_ORDER = 1,
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parameter MIN_STAGE = 0,
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parameter NUM_STAGES = 2,
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parameter PACK = 0
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) (
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input [PORT_ADDRESS_WIDTH-1:0] rotate,
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input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count,
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output [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl
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);
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/*
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* This module computes the control bits that are used to configure the MUXes
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* in the pack interconect network. The controls are configured according to
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* the specified global rotation and the prefix count of each of the outputs.
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*/
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localparam NUM_OF_PORTS = 2**PORT_ADDRESS_WIDTH;
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wire [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl1;
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reg [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl2;
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generate
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genvar i, j, k;
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integer n;
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localparam z = 2**MUX_ORDER;
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/* This part is magic */
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for (i = 0; i < NUM_STAGES; i = i + 1) begin: ctrl_gen_outer
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localparam k0 = 2**(PORT_ADDRESS_WIDTH - MUX_ORDER*(i+1)-MIN_STAGE);
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localparam k1 = 2**(MUX_ORDER*(1+i)+MIN_STAGE);
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for (j = 0; j < NUM_OF_PORTS; j = j + 1) begin: ctrl_gen_inner
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/* Offset in the ctrl signal */
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localparam s = (i*NUM_OF_PORTS+j)*MUX_ORDER;
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localparam m = (j % k1) * k0;
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localparam n = j / k1;
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if (MUX_ORDER == 1 && j % 2 == 0) begin
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/* This is an optimization that only works for 2:1 MUXes */
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assign ctrl1[s] = ~ctrl1[s+1];
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end else begin
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assign ctrl1[s+:MUX_ORDER] = (j - (prefix_count[m*PORT_ADDRESS_WIDTH+:PORT_ADDRESS_WIDTH] + n - rotate) / k0) % z;
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end
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end
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end
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if (PACK == 0 || MUX_ORDER == 1) begin
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/* For 2:1 MUXes pack and unpack control is the same */
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assign ctrl = ctrl1;
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end else begin
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/*
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* Transform demux control into mux control. The implementation here uses a
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* priority encoder.
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*/
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for (i = 0; i < NUM_STAGES*NUM_OF_PORTS; i = i + z) begin: demux_gen_outer
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localparam base = i*MUX_ORDER;
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for (k = 0; k < z; k = k + 1) begin: demux_gen_inner
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always @(ctrl1) begin
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ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= {MUX_ORDER{1'b1}};
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for (n = 0; n < z; n = n + 1) begin
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if (ctrl1[base+n*MUX_ORDER+:MUX_ORDER] == k) begin
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ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= n[MUX_ORDER-1:0];
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end
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end
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end
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end
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end
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assign ctrl = ctrl2;
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end
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endgenerate
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endmodule
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