Archived
102 lines
2.3 KiB
Verilog
102 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/03/21 18:35:38
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// Design Name:
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// Module Name: tx_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_control
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(
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input sys_clk , // 122.88MHz
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input sys_rst ,
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input sig_clk , // 48MHz
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input sig_rst ,
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output [15:0] tx_data_i ,
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output [15:0] tx_data_q ,
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// debug ports
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input [ 2:0] waveform_sel ,
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input sweep_on ,
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input [31:0] freq_set ,
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input [ 1:0] iq_sel ,
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input [ 3:0] bb_rshift
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);
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// pn seq
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wire [15:0] tx_pn_seq_i;
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wire [15:0] tx_pn_seq_q;
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tx_pn_seq_6mcps #(
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.DATA_WIDTH (16)
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) u_tx_pn_seq
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(
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.sys_clk (sys_clk ), // 122.88MHz
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.sys_rst (sys_rst ),
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.sig_clk (sig_clk ), // 48MHz
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.sig_rst (sig_rst ),
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.tx_data_i (tx_pn_seq_i),
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.tx_data_q (tx_pn_seq_q)
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);
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// qpsk
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wire [15:0] tx_qpsk_i;
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wire [15:0] tx_qpsk_q;
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tx_qpsk #(
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.DATA_WIDTH (16 ),
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.SQUARE_INTERP (32 ),
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.CLK_FREQ (122880000 )
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) u_tx_qpsk
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(
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.clk (sys_clk ),
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.rst (sys_rst ),
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.tx_data_i (tx_qpsk_i ),
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.tx_data_q (tx_qpsk_q ),
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// debug ports
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.waveform_sel (waveform_sel[1:0] ),
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.sweep_on (sweep_on ),
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.freq_set (freq_set ),
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.iq_sel (iq_sel ),
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.bb_rshift (bb_rshift )
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);
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// output
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reg [15:0] tx_data_buf_i = 'b0;
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reg [15:0] tx_data_buf_q = 'b0;
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assign tx_data_i = tx_data_buf_i;
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assign tx_data_q = tx_data_buf_q;
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always @(posedge sys_clk) begin
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if (sys_rst) begin
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tx_data_buf_i <= 'b0;
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tx_data_buf_q <= 'b0;
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end
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else if (waveform_sel[2]) begin
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tx_data_buf_i <= tx_pn_seq_i;
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tx_data_buf_q <= tx_pn_seq_q;
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end
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else begin
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tx_data_buf_i <= tx_qpsk_i;
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tx_data_buf_q <= tx_qpsk_q;
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end
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end
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endmodule
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