Archived
27 lines
827 B
Tcl
27 lines
827 B
Tcl
set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set data_clk [get_clocks -of_objects [get_ports data_clk_i]]
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set_property ASYNC_REG TRUE \
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[get_cells -hier cdc_sync_stage1_*_reg] \
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[get_cells -hier cdc_sync_stage2_*_reg]
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set_false_path \
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-from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \
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-to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}]
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# TX FIFO
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set_max_delay \
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-from $ctrl_clk \
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-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *tx_sync*}] \
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[get_property PERIOD $data_clk] -datapath_only
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# RX FIFO
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set_max_delay \
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-from $data_clk \
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-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *rx_sync*}] \
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[get_property PERIOD $ctrl_clk] -datapath_only
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# Reset
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set_false_path \
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-to [get_pins -hier data_reset_vec_reg*/PRE]
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