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vivado-202304/projects/duifei/common_ipi-bd/basic_driver_bd/system_bd.bxml
T
josh 02685d9802 reconstruct project directory
create common_ip and common_ipi-bd to minimize local storage
2023-04-13 12:04:41 +08:00

107 lines
5.4 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<Root MajorVersion="0" MinorVersion="37">
<CompositeFile CompositeFileTopName="system_bd" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1680163503"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1680163503"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1680163503"/>
<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1680163503"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect/s00_couplers/auto_pc"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_axi_interconnect_0/system_bd_axi_interconnect_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci" Type="IP">
<Instance HierarchyPath="axi_spi_engine/axi_spi_engine"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0.xci" Type="IP">
<Instance HierarchyPath="axi_spi_engine/spi_engine_execution"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_ps_system_0/system_bd_ps_system_0.xci" Type="IP">
<Instance HierarchyPath="ps_system"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0.xci" Type="IP">
<Instance HierarchyPath="rst_ps_system_50M"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_bd_xlconcat_irpt_0/system_bd_xlconcat_irpt_0.xci" Type="IP">
<Instance HierarchyPath="xlconcat_irpt"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="synth/system_bd.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
</File>
<File Name="sim/system_bd.v" Type="Verilog">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="system_bd_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="OUT_OF_CONTEXT"/>
</File>
<File Name="hw_handoff/system_bd.hwh" Type="HwHandoff">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="hw_handoff/system_bd_bd.tcl">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="synth/system_bd.hwdef">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="HW_HANDOFF"/>
</File>
<File Name="sim/system_bd.protoinst">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SIMULATION"/>
</File>
</FileCollection>
</CompositeFile>
</Root>