Archived
147 lines
4.5 KiB
Verilog
147 lines
4.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_upack2_impl #(
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parameter NUM_OF_CHANNELS = 4,
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parameter SAMPLES_PER_CHANNEL = 1,
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parameter SAMPLE_DATA_WIDTH = 16
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) (
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input clk,
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input reset,
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input [NUM_OF_CHANNELS-1:0] enable,
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input [NUM_OF_CHANNELS-1:0] fifo_rd_en,
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output reg fifo_rd_valid,
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output reg fifo_rd_underflow,
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output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data,
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input s_axis_valid,
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output s_axis_ready,
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input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data
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);
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/*
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* Final output data of the routing network that will be written to
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* `fifo_rd_data` after being deinterleaved.
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*/
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wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data;
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/*
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* Deinterleaved version of `out_data`
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*/
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wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] deinterleaved_data;
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/*
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* Internal read signal.
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*/
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wire data_rd_en;
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/*
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* Control signals from/to the pack shell.
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*/
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wire ce;
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wire ready;
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wire reset_data;
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/*
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* Only the first signal of fifo_rd_en is used. All others are ignored. The
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* only reason why fifo_rd_en has multiple entries is to keep the interface
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* somewhat backwards compatible to the previous upack.
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*/
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assign data_rd_en = fifo_rd_en[0];
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assign ce = s_axis_valid & data_rd_en;
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assign s_axis_ready = ready & ce;
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pack_shell #(
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.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
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.SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL),
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.SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH),
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.PACK (0)
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) i_pack_shell (
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.clk (clk),
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.reset (reset),
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.reset_data (reset_data),
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.enable (enable),
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.ce (ce),
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.ready (ready),
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.in_data (s_axis_data),
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.out_data (out_data),
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.out_valid (),
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.out_sync ()
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);
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/*
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* Data at the output of the routing network is interleaved. The upack
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* core is supposed to produce deinterleaved data. This just rearrange the
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* bits in the data vector and does not consume any FPGA resources.
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*/
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ad_perfect_shuffle #(
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.NUM_GROUPS (SAMPLES_PER_CHANNEL),
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.WORDS_PER_GROUP (NUM_OF_CHANNELS),
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.WORD_WIDTH (SAMPLE_DATA_WIDTH)
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) i_deinterleave (
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.data_in (out_data),
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.data_out (deinterleaved_data)
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);
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always @(posedge clk) begin
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/* In case of an underflow the output vector should be zeroed */
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if (reset_data == 1'b1 ||
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(data_rd_en == 1'b1 && s_axis_valid == 1'b0)) begin
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fifo_rd_data <= 'h00;
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end else if (data_rd_en == 1'b1) begin
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fifo_rd_data <= deinterleaved_data;
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end
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end
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always @(posedge clk) begin
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if (data_rd_en == 1'b1) begin
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fifo_rd_valid <= s_axis_valid & ~reset_data;
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fifo_rd_underflow <= ~(s_axis_valid & ~reset_data);
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end else begin
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fifo_rd_valid <= 1'b0;
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fifo_rd_underflow <= 1'b0;
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end
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end
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endmodule
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