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josh
cd256a8cd6
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64 lines
1.4 KiB
Verilog
64 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2022/08/26 16:14:01
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// Design Name:
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// Module Name: glink_rst_create
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module glink_rst_create(
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input glink_logic_clk,
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input i_reset_p,
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output reset_p
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);
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wire rst_n_fil;
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reset_filter
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#(
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.RESET_MANUAL_POL (0 ),
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.RESET_POWER_POL (1 ),
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.RESET_OUT_POL (0 ),
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.FILTER_WIDTH (125),
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.RESET_MANUAL_EN_POL (1 )
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)
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u_reset_filter
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(
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.clk (glink_logic_clk),
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.i_reset_p (i_reset_p ),
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.i_reset_m_en (1'b0 ),
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.i_reset_m (1'b1 ),
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.o_reset_p_syn ( ),
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.o_reset_combo (rst_n_fil )
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);
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reset_pls_extend
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#(
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.IN_POLARITY (0 ),
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.OUT_POLARITY (1 ),
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.EXTEND_WIDTH (2500000)
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)
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u_reset_pls_extend
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(
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.clk (glink_logic_clk),
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.i_reset (rst_n_fil ),
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.o_reset (reset_p )
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);
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endmodule
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