Archived
172 lines
4.4 KiB
Verilog
172 lines
4.4 KiB
Verilog
|
|
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 2020/09/02 10:48:55
|
|
// Design Name:
|
|
// Module Name: d
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool Versions:
|
|
// Description:
|
|
// SPI时钟频率50MHz。每一帧数据12个字节，共96bit数据。
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
module spi_slave#(
|
|
parameter BIT_NUM = 96
|
|
)
|
|
(
|
|
input i_sys_clk,
|
|
input i_sys_rst_n,
|
|
|
|
input i_spi_sck, //从机在时钟下降沿采样数据
|
|
input i_spi_cs, //低电平时从机接收数据指令
|
|
input i_spi_sdi,
|
|
output [31:0] o_frame_count, //帧计数
|
|
output [15:0] o_fre_code , //天线频率
|
|
output [7:0] o_tx_mgc, //发射MGC
|
|
output [3:0] o_model, //模式字
|
|
output [3:0] o_rf_en, //射频使能
|
|
output [3:0] o_cal1_mgc, //接收校准1mgc
|
|
output [3:0] o_cal2_mgc, //接收校准2mgc
|
|
output [3:0] o_cal3_mgc, //接收校准3mgc
|
|
output [3:0] o_cal4_mgc, //接收校准4mgc
|
|
output [7:0] o_tx_cal_mgc, //发射校准mgc
|
|
output [7:0] o_rx1_mgc, //接收1mgc
|
|
output [7:0] o_rx2_mgc, //接收2mgc
|
|
output [7:0] o_rx3_mgc, //接收3mgc
|
|
output [7:0] o_rx4_mgc , //接收4mgc
|
|
|
|
output [3:0] o_ceshi_model
|
|
);
|
|
|
|
reg [BIT_NUM -1:0] receive_data;
|
|
reg [3:0] rf_en ;
|
|
reg [3:0] model;
|
|
reg [31:0] frame_count;
|
|
reg [11:0] fre_code;
|
|
reg [7:0] tx_mgc;
|
|
reg [7:0] rx1_mgc;
|
|
reg [7:0] rx2_mgc;
|
|
reg [7:0] rx3_mgc;
|
|
reg [7:0] rx4_mgc;
|
|
reg [3:0] cal1_mgc;
|
|
reg [3:0] cal2_mgc;
|
|
reg [3:0] cal3_mgc;
|
|
reg [3:0] cal4_mgc;
|
|
reg [7:0] tx_cal_mgc;
|
|
reg [3:0] ceshi_module;
|
|
|
|
|
|
assign o_frame_count= frame_count;
|
|
assign o_fre_code = {4'b0,fre_code};
|
|
assign o_rf_en = rf_en;
|
|
assign o_model = model;
|
|
assign o_tx_mgc = tx_mgc;
|
|
assign o_cal1_mgc = cal1_mgc;
|
|
assign o_cal2_mgc = cal2_mgc;
|
|
assign o_cal3_mgc = cal3_mgc;
|
|
assign o_cal4_mgc = cal4_mgc;
|
|
assign o_tx_cal_mgc = tx_cal_mgc;
|
|
assign o_rx1_mgc = rx1_mgc;
|
|
assign o_rx2_mgc = rx2_mgc;
|
|
assign o_rx3_mgc = rx3_mgc;
|
|
assign o_rx4_mgc = rx4_mgc;
|
|
assign o_ceshi_model = ceshi_module;
|
|
|
|
always @ ( negedge i_spi_sck or negedge i_sys_rst_n)begin
|
|
if( !i_sys_rst_n )
|
|
receive_data <= 'b0;
|
|
else if(i_spi_cs == 1'b0)
|
|
receive_data <= {receive_data,i_spi_sdi};
|
|
else
|
|
receive_data <= receive_data;
|
|
end
|
|
|
|
|
|
reg [2:0] cs_reg;
|
|
|
|
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
|
if( !i_sys_rst_n )
|
|
cs_reg <= 3'b111;
|
|
else
|
|
cs_reg <= {cs_reg[1:0],i_spi_cs};
|
|
end
|
|
|
|
|
|
|
|
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)begin
|
|
tx_cal_mgc<=8'h0;
|
|
end
|
|
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin
|
|
tx_cal_mgc<=receive_data[15:8];
|
|
end
|
|
else begin
|
|
tx_cal_mgc<=tx_cal_mgc;
|
|
end
|
|
end
|
|
|
|
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)begin
|
|
fre_code <= 12'h6d6;
|
|
tx_mgc <= 8'h00;
|
|
rf_en <= 4'b1;
|
|
model <= 4'b0;
|
|
frame_count <= 32'd1;
|
|
rx1_mgc <= 4'h0;
|
|
rx2_mgc <= 4'h0;
|
|
rx3_mgc <= 4'h0;
|
|
rx4_mgc <= 4'h0;
|
|
cal1_mgc <= 4'h0;
|
|
cal2_mgc <= 4'h0;
|
|
cal3_mgc <= 4'h0;
|
|
cal4_mgc <= 4'h0;
|
|
ceshi_module <= 4'h0;
|
|
end
|
|
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin
|
|
frame_count <= frame_count+1'b1;
|
|
rf_en <= receive_data[87:84];
|
|
model <= receive_data[83:80];
|
|
ceshi_module<= receive_data[79:76];
|
|
fre_code <= receive_data[75:64];
|
|
tx_mgc <= receive_data[63:56];
|
|
cal1_mgc <= receive_data[55:52];
|
|
cal2_mgc <= receive_data[51:48];
|
|
cal3_mgc <= receive_data[47:44];
|
|
cal4_mgc <= receive_data[43:40];
|
|
rx1_mgc <= receive_data[39:32];
|
|
rx2_mgc <= receive_data[31:24];
|
|
rx3_mgc <= receive_data[23:16];
|
|
rx4_mgc <= receive_data[15:8];
|
|
end
|
|
else begin
|
|
frame_count <= frame_count ;
|
|
rf_en <= rf_en ;
|
|
model <= model ;
|
|
fre_code <= fre_code ;
|
|
tx_mgc <= tx_mgc ;
|
|
cal1_mgc <= cal1_mgc ;
|
|
cal2_mgc <= cal2_mgc ;
|
|
cal3_mgc <= cal3_mgc ;
|
|
cal4_mgc <= cal4_mgc ;
|
|
rx1_mgc <= rx1_mgc ;
|
|
rx2_mgc <= rx2_mgc ;
|
|
rx3_mgc <= rx3_mgc ;
|
|
rx4_mgc <= rx4_mgc ;
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
|