Archived
3001 lines
389 KiB
Plaintext
3001 lines
389 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2019.1.3 (64-bit)
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# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
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# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
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# Start of session at: Wed Dec 8 20:25:24 2021
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# Process ID: 146145
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# Current directory: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr
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# Command line: vivado -mode batch -source axi_adxcvr_ip.tcl
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# Log file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.log
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# Journal file: /home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr/vivado.jou
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#-----------------------------------------------------------
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source axi_adxcvr_ip.tcl
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# source ../../scripts/adi_env.tcl
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## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
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## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
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## if [info exists ::env(ADI_HDL_DIR)] {
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## set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
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## }
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## if [info exists ::env(ADI_GHDL_DIR)] {
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## set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
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## }
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# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
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### variable auto_set_param_list
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### variable auto_set_param_list_overwritable
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### variable fpga_series_list
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### variable fpga_family_list
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### variable speed_grade_list
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### variable dev_package_list
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### variable xcvr_type_list
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### variable fpga_voltage_list
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### set auto_set_param_list { \
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### DEV_PACKAGE \
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### SPEED_GRADE \
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### FPGA_FAMILY \
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### FPGA_TECHNOLOGY }
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### set auto_set_param_list_overwritable { \
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### FPGA_VOLTAGE \
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### XCVR_TYPE }
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### set fpga_technology_list { \
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### { Unknown 0 } \
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### { 7series 1 } \
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### { ultrascale 2 } \
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### { ultrascale+ 3 }}
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### set fpga_family_list { \
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### { Unknown 0 } \
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### { artix 1 } \
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### { kintex 2 } \
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### { virtex 3 } \
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### { zynq 4 }}
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### set speed_grade_list { \
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### { Unknown 0 } \
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### { -1 10 } \
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### { -1L 11 } \
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### { -1H 12 } \
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### { -1HV 13 } \
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### { -1LV 14 } \
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### { -2 20 } \
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### { -2L 21 } \
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### { -2LV 22 } \
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### { -3 30 }}
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### set dev_package_list { \
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### { Unknown 0 } \
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### { rf 1 } \
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### { fl 2 } \
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### { ff 3 } \
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### { fb 4 } \
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### { hc 5 } \
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### { fh 6 } \
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### { cs 7 } \
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### { cp 8 } \
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### { ft 9 } \
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### { fg 10 } \
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### { sb 11 } \
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### { rb 12 } \
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### { rs 13 } \
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### { cl 14 } \
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### { sf 15 } \
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### { ba 16 } \
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### { fa 17 } \
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### { fs 18 } \
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### { fi 19 }}
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### set xcvr_type_list { \
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### { Unknown 0 } \
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### { GTPE2_NOT_SUPPORTED 1 } \
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### { GTXE2 2 } \
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### { GTHE2_NOT_SUPPORTED 3 } \
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### { GTZE2_NOT_SUPPORTED 4 } \
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### { GTHE3 5 } \
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### { GTYE3_NOT_SUPPORTED 6 } \
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### { GTRE4_NOT_SUPPORTED 7 } \
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### { GTHE4 8 } \
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### { GTYE4 9 } \
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### { GTME4_NOT_SUPPORTED 10}}
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### set fpga_voltage_list {0 5000} ;
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### proc adi_device_spec {cellpath param} {
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###
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### set list_pointer [string tolower $param]
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### set list_pointer [append list_pointer "_list"]
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###
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### upvar 1 $list_pointer $list_pointer
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###
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### set ip [get_bd_cells $cellpath]
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### set part [get_property PART [current_project]]
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###
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### switch -regexp -- $param {
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### FPGA_TECHNOLOGY {
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### switch -regexp -- $part {
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### ^xc7 {set series_name 7series}
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### ^xczu {set series_name ultrascale+}
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### ^xc.u.p {set series_name ultrascale+}
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### ^xc.u {set series_name ultrascale }
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### default {
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### puts "Undefined fpga technology for \"$part\"!"
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### exit -1
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### }
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### }
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### return "$series_name"
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### }
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### FPGA_FAMILY {
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### set fpga_family [get_property FAMILY $part]
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### foreach i $fpga_family_list {
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### regexp ^[lindex $i 0] $fpga_family matched
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### }
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### return "$matched"
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### }
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### SPEED_GRADE {
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### set speed_grade [get_property SPEED $part]
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### return "$speed_grade"
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### }
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### DEV_PACKAGE {
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### set dev_package [get_property PACKAGE $part]
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### foreach i $dev_package_list {
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### regexp ^[lindex $i 0] $dev_package matched
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### }
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### return "$matched"
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### }
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### XCVR_TYPE {
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### set matched ""
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### set dev_transcivers "none"
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### foreach x [list_property $part] {
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### regexp ^GT..._TRANSCEIVERS $x dev_transcivers
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### }
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### foreach i $xcvr_type_list {
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### regexp ^[lindex $i 0] $dev_transcivers matched
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### }
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### if { $matched eq "" } {
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### puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
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### }
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### return "$matched"
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### }
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### FPGA_VOLTAGE {
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### set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
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### set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
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###
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### return "$fpga_voltage"
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### }
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### default {
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### puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
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### }
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### }
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### }
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## if {![info exists REQUIRED_VIVADO_VERSION]} {
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## set REQUIRED_VIVADO_VERSION "2019.1"
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## }
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## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
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## set IGNORE_VERSION_CHECK 1
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## } elseif {![info exists IGNORE_VERSION_CHECK]} {
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## set IGNORE_VERSION_CHECK 0
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## }
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## proc adi_ip_ttcl {ip_name ip_constr_files} {
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##
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## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
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## set f [ipx::add_file $ip_constr_files $proj_filegroup]
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## set_property -dict [list \
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## type ttcl \
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## ] $f
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## ipx::reorder_files -front $ip_constr_files $proj_filegroup
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## }
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## proc adi_ip_sim_ttcl {ip_name ip_files} {
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##
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## set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
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## set f [ipx::add_file $ip_files $proj_filegroup]
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## set_property -dict [list \
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## type ttcl \
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## ] $f
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## ipx::reorder_files -front $ip_files $proj_filegroup
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## }
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## proc adi_ip_bd {ip_name ip_bd_files} {
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## set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
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## if {$proj_filegroup == {}} {
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## set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
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## }
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##
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## foreach file $ip_bd_files {
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## set f [ipx::add_file $file $proj_filegroup]
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## set_property -dict [list \
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## type tclSource \
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## ] $f
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## }
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## }
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## proc adi_ip_infer_streaming_interfaces {ip_name} {
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##
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## ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
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##
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## }
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## proc adi_ip_infer_mm_interfaces {ip_name} {
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##
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## ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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##
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## }
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## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
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## foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
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## set_property ENABLEMENT_DEPENDENCY $dependency $port
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## if {$driver_value != {}} {
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## set_property DRIVER_VALUE $driver_value $port
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## }
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## }
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## }
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## proc adi_set_bus_dependency {bus prefix dependency} {
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## set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
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## adi_set_ports_dependency $prefix $dependency 0
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## }
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## proc adi_add_port_map {bus phys logic} {
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## set map [ipx::add_port_map $phys $bus]
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## set_property "PHYSICAL_NAME" $phys $map
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## set_property "LOGICAL_NAME" $logic $map
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## }
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## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
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## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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##
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## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
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## set_property "BUS_TYPE_VLNV" $bus_type $bus
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## set_property "INTERFACE_MODE" $mode $bus
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##
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## foreach port_map $port_maps {
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## adi_add_port_map $bus {*}$port_map
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## }
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## }
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## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
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## for {set i 0} {$i < $num} {incr i} {
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## set bus_name [format "%s%d" $bus_name_prefix $i]
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## set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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##
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## set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
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## set_property "BUS_TYPE_VLNV" $bus_type $bus
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## set_property "INTERFACE_MODE" $mode $bus
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##
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## if {$dependency ne ""} {
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## set bus_dependency [string map [list "{i}" $i] $dependency]
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## set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
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## }
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##
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## foreach port_map $port_maps {
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## lassign $port_map phys logic width width_dep
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## set map [ipx::add_port_map $phys $bus]
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## set_property "PHYSICAL_NAME" $phys $map
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## set_property "LOGICAL_NAME" $logic $map
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## set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
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## set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
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## if {$width_dep ne ""} {
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## set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map
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## set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map
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## set width_dep_r "(($width_dep) * $i)"
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## set width_dep_l "(($width_dep) * ($i + 1)-1)"
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## set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map
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## set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map
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## }
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## }
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## }
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## }
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## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
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## set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
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## set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
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## set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
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## set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
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## set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
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## set_property display_name $clock_inf_name $clock_inf
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## set clock_map [ipx::add_port_map "CLK" $clock_inf]
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## set_property physical_name $clock_signal_name $clock_map
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##
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## set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
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## set_property value $bus_inf_name $assoc_busif
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##
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## if { $reset_signal_name != "" } {
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## set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
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## set_property value $reset_signal_name $assoc_reset
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##
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## set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
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## set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
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## set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
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## set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
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## set_property display_name $reset_inf_name $reset_inf
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## set_property interface_mode $reset_signal_mode $reset_inf
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## set reset_map [ipx::add_port_map "RST" $reset_inf]
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## set_property physical_name $reset_signal_name $reset_map
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##
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## set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
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## if {[string match {*[Nn]} $reset_signal_name] == 1} {
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## set_property value "ACTIVE_LOW" $reset_polarity
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## } else {
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## set_property value "ACTIVE_HIGH" $reset_polarity
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## }
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## }
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## }
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## proc adi_ip_add_core_dependencies {vlnvs} {
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## foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
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## foreach vlnv $vlnvs {
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## ipx::add_subcore $vlnv $file_group
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## }
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## }
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## }
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## proc adi_ip_create {ip_name} {
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##
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## global ad_hdl_dir
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## global ad_ghdl_dir
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## global REQUIRED_VIVADO_VERSION
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## global IGNORE_VERSION_CHECK
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##
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## set VIVADO_VERSION [version -short]
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## if {$IGNORE_VERSION_CHECK} {
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## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
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## puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
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## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
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## puts -nonewline "got $VIVADO_VERSION.\n"
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## }
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## } else {
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## if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
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## puts -nonewline "ERROR: vivado version mismatch; "
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## puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
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## puts -nonewline "got $VIVADO_VERSION.\n"
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## puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
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## exit 2
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## }
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## }
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##
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## create_project $ip_name . -force
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##
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## ## Load custom message severity definitions
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## source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
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##
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## set lib_dirs $ad_hdl_dir/library
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## if {$ad_hdl_dir ne $ad_ghdl_dir} {
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## lappend lib_dirs $ad_ghdl_dir/library
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## }
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##
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## set_property ip_repo_paths $lib_dirs [current_fileset]
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## update_ip_catalog
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## }
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## proc adi_ip_files {ip_name ip_files} {
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## set proj_fileset [get_filesets sources_1]
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## foreach m_file $ip_files {
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## if {[file extension $m_file] eq ".xdc"} {
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## add_files -norecurse -fileset constrs_1 $m_file
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## } else {
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## add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file
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## }
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## }
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## set_property "top" "$ip_name" $proj_fileset
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## }
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## proc adi_ip_properties_lite {ip_name} {
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##
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## global ad_hdl_dir
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##
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## ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
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##
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## set_property name $ip_name [ipx::current_core]
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##
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## set_property vendor_display_name {Analog Devices} [ipx::current_core]
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## set_property company_url {http://www.analog.com} [ipx::current_core]
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##
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## set i_families ""
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## foreach i_part [get_parts] {
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## lappend i_families [get_property FAMILY $i_part]
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## }
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## set i_families [lsort -unique $i_families]
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## set s_families [get_property supported_families [ipx::current_core]]
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## foreach i_family $i_families {
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## set s_families "$s_families $i_family Production"
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## set s_families "$s_families $i_family Beta"
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## }
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## set_property supported_families $s_families [ipx::current_core]
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##
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## ipx::save_core [ipx::current_core]
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##
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## ipx::remove_all_bus_interface [ipx::current_core]
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## set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
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## foreach map $memory_maps {
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## ipx::remove_memory_map [lindex $map 2] [ipx::current_core]
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## }
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##
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## ipx::update_checksums [ipx::current_core]
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## ipx::save_core [ipx::current_core]
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## }
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## proc adi_ip_properties {ip_name} {
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##
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## adi_ip_properties_lite $ip_name
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##
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## ipx::infer_bus_interface {\
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## s_axi_awvalid \
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## s_axi_awaddr \
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## s_axi_awprot \
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## s_axi_awready \
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## s_axi_wvalid \
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## s_axi_wdata \
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## s_axi_wstrb \
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## s_axi_wready \
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## s_axi_bvalid \
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## s_axi_bresp \
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##
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## s_axi_bready \
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## s_axi_arvalid \
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## s_axi_araddr \
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## s_axi_arprot \
|
|
## s_axi_arready \
|
|
## s_axi_rvalid \
|
|
## s_axi_rdata \
|
|
## s_axi_rresp \
|
|
## s_axi_rready} \
|
|
## xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
|
|
##
|
|
## ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
|
## ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
|
##
|
|
## set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
|
|
## set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
|
|
##
|
|
## if {$raddr_width != $waddr_width} {
|
|
## puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
|
|
## set range 65536
|
|
## } else {
|
|
## if {$raddr_width >= 16} {
|
|
## set range 65536
|
|
## } else {
|
|
## set range [expr 1 << $raddr_width]
|
|
## }
|
|
## }
|
|
##
|
|
## ipx::add_memory_map {s_axi} [ipx::current_core]
|
|
## set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
|
|
## ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
|
|
## set_property range $range [ipx::get_address_blocks axi_lite \
|
|
## -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
|
|
## ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
|
|
## ipx::save_core
|
|
## }
|
|
## proc adi_init_bd_tcl {} {
|
|
##
|
|
## global auto_set_param_list
|
|
## global auto_set_param_list_overwritable
|
|
## set cc [ipx::current_core]
|
|
##
|
|
## if { [file exists bd] } {
|
|
## file delete -force bd
|
|
## }
|
|
## file mkdir bd
|
|
##
|
|
## set bd_tcl [open "bd/bd.tcl" w]
|
|
##
|
|
## puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
|
|
## puts $bd_tcl "proc init {cellpath otherInfo} {"
|
|
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
|
## puts $bd_tcl ""
|
|
## set auto_set_param ""
|
|
## foreach i $auto_set_param_list {
|
|
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
|
## append auto_set_param " $i \\\n"
|
|
## }
|
|
## }
|
|
## if { $auto_set_param ne "" } {
|
|
## puts $bd_tcl " bd::mark_propagate_only \$ip \" \\"
|
|
## regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
|
|
## puts $bd_tcl $auto_set_param
|
|
## }
|
|
##
|
|
## set auto_set_overwritable_param ""
|
|
## foreach i $auto_set_param_list_overwritable {
|
|
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
|
|
## append auto_set_overwritable_param " $i \\\n"
|
|
## }
|
|
## }
|
|
## if { $auto_set_overwritable_param ne "" } {
|
|
## puts $bd_tcl " bd::mark_propagate_override \$ip \" \\"
|
|
## regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
|
|
## puts $bd_tcl $auto_set_overwritable_param
|
|
## }
|
|
## puts $bd_tcl " adi_auto_assign_device_spec \$cellpath"
|
|
## puts $bd_tcl "}"
|
|
## puts $bd_tcl ""
|
|
## puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
|
|
## puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
|
|
## puts $bd_tcl ""
|
|
## puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]"
|
|
## puts $bd_tcl " set ip_param_list \[list_property \$ip\]"
|
|
## puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
|
|
## puts $bd_tcl ""
|
|
## puts $bd_tcl " set parent_dir \"../\""
|
|
## puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {"
|
|
## puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
|
|
## puts $bd_tcl " if { \[file exists \$linkname\] } {"
|
|
## puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
|
|
## puts $bd_tcl " break"
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl " append parent_dir \"../\""
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl ""
|
|
## puts $bd_tcl " # Find predefindes auto assignable parameters"
|
|
## puts $bd_tcl " foreach i \$auto_set_param_list {"
|
|
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
|
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
|
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl ""
|
|
## puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters"
|
|
## puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {"
|
|
## puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
|
|
## puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]"
|
|
## puts $bd_tcl " set_property CONFIG.\$i \$val \$ip"
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl " }"
|
|
## puts $bd_tcl "}"
|
|
## puts $bd_tcl ""
|
|
## close $bd_tcl
|
|
##
|
|
## set proj_fileset [get_filesets sources_1]
|
|
## add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
|
|
##
|
|
## set local_mk [open "temporary_case_dependencies.mk" w]
|
|
## seek $local_mk 0 start
|
|
## puts $local_mk "CLEAN_TARGET += bd"
|
|
## puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
|
|
## close $local_mk
|
|
## }
|
|
## proc adi_add_auto_fpga_spec_params {} {
|
|
##
|
|
## global auto_set_param_list
|
|
## global auto_set_param_list_overwritable
|
|
## set cc [ipx::current_core]
|
|
##
|
|
## foreach i $auto_set_param_list {
|
|
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
|
## adi_add_device_spec_param $i
|
|
## }
|
|
## }
|
|
## foreach i $auto_set_param_list_overwritable {
|
|
## if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
|
|
## adi_add_device_spec_param $i
|
|
## }
|
|
## }
|
|
## }
|
|
## proc adi_add_device_spec_param {ip_param} {
|
|
##
|
|
## set cc [ipx::current_core]
|
|
##
|
|
## set list_pointer [string tolower $ip_param]
|
|
## set list_pointer [append list_pointer "_list"]
|
|
##
|
|
## global $list_pointer
|
|
##
|
|
## # set j 1D list from the original list
|
|
## foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
|
|
##
|
|
## # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
|
|
## if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
|
|
## set_property -dict [list \
|
|
## "value_validation_type" "range_long" \
|
|
## "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
|
|
## "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
|
|
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
|
## } else {
|
|
## set_property -dict [list \
|
|
## "value_validation_type" "pairs" \
|
|
## "value_validation_pairs" $j ] \
|
|
## [ipx::get_user_parameters $ip_param -of_objects $cc]
|
|
## }
|
|
##
|
|
## # FPGA info grup
|
|
## set info_group_name "FPGA info"
|
|
## set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
|
|
## if { [string trim $info_group] eq "" } {
|
|
## set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
|
## set info_group [ipgui::add_group -name $info_group_name -component $cc \
|
|
## -parent $page0 -display_name $info_group_name]
|
|
## }
|
|
##
|
|
## set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
|
|
## set_property -dict [list "widget" "comboBox" ] $p
|
|
## ipgui::move_param -component $cc -order 0 $p -parent $info_group
|
|
## }
|
|
## proc adi_if_define {name} {
|
|
##
|
|
## ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
|
|
## ipx::create_bus_definition analog.com interface $name 1.0
|
|
##
|
|
## set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
|
|
## set_property xml_file_name ${name}.xml [ipx::current_busdef]
|
|
## set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
|
|
##
|
|
## ipx::save_abstraction_definition [ipx::current_busabs]
|
|
## ipx::save_bus_definition [ipx::current_busdef]
|
|
## }
|
|
## proc adi_if_ports {dir width name {type none}} {
|
|
##
|
|
## ipx::add_bus_abstraction_port $name [ipx::current_busabs]
|
|
## set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
|
|
## set_property master_presence required $m_intf
|
|
## set_property slave_presence required $m_intf
|
|
## set_property master_width $width $m_intf
|
|
## set_property slave_width $width $m_intf
|
|
##
|
|
## set m_dir "in"
|
|
## set s_dir "out"
|
|
## if {$dir eq "output"} {
|
|
## set m_dir "out"
|
|
## set s_dir "in"
|
|
## }
|
|
##
|
|
## set_property master_direction $m_dir $m_intf
|
|
## set_property slave_direction $s_dir $m_intf
|
|
##
|
|
## if {$type ne "none"} {
|
|
## set_property is_${type} true $m_intf
|
|
## }
|
|
##
|
|
## ipx::save_bus_definition [ipx::current_busdef]
|
|
## ipx::save_abstraction_definition [ipx::current_busabs]
|
|
## }
|
|
## proc adi_if_infer_bus {if_name mode name maps} {
|
|
##
|
|
## ipx::add_bus_interface $name [ipx::current_core]
|
|
## set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
|
|
## set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
|
|
## set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
|
|
## set_property interface_mode $mode $m_bus_if
|
|
##
|
|
## foreach map $maps {
|
|
## set m_maps [regexp -all -inline {\S+} $map]
|
|
## lassign $m_maps p_name p_map
|
|
## ipx::add_port_map $p_name $m_bus_if
|
|
## set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
|
|
## }
|
|
## }
|
|
# adi_ip_create axi_adxcvr
|
|
CRITICAL WARNING: vivado version mismatch; expected 2019.1, got 2019.1.3.
|
|
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
|
|
## set_msg_config -id {BD 41-1343} -new_severity WARNING
|
|
## set_msg_config -id {BD 41-1306} -new_severity WARNING
|
|
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
|
|
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
|
|
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
|
|
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
|
|
## set_msg_config -id {Synth 8-3331} -new_severity INFO
|
|
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
|
|
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
|
|
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
|
|
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
|
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library'.
|
|
INFO: [IP_Flow 19-3656] If you move the project, the path for repository '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'.)
|
|
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/gatsby/Workspace/Vivado2019.1/ADI/ghdl/library'; Can't find the specified path.
|
|
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
|
|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2019.1/data/ip'.
|
|
# adi_ip_files axi_adxcvr [list \
|
|
# "$ad_hdl_dir/library/common/up_axi.v" \
|
|
# "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
|
|
# "axi_adxcvr_es.v" \
|
|
# "axi_adxcvr_up.v" \
|
|
# "axi_adxcvr_mdrp.v" \
|
|
# "axi_adxcvr_mstatus.v" \
|
|
# "axi_adxcvr.v" ]
|
|
# adi_ip_properties axi_adxcvr
|
|
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
|
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
|
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/common/up_axi.v' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
|
INFO: [IP_Flow 19-459] IP file '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/scripts/adi_xilinx_device_info_enc.tcl' appears to be outside of the project area '/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/axi_adxcvr'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
|
|
INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
WARNING: [IP_Flow 19-5463] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type master.
|
|
INFO: [Common 17-14] Message 'IP_Flow 19-5463' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_16' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_17' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_18' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_19' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_20' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_21' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_22' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_23' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_24' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_25' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_26' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_27' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_28' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_29' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port enb on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port addr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port wr on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
WARNING: [IP_Flow 19-5464] No port map found for required logical port ready on bus interface abstraction if_xcvr_cm_rtl for interface type slave.
|
|
INFO: [Common 17-14] Message 'IP_Flow 19-5464' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_30' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_31' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_ch_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_cm_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_0' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_1' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_10' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_11' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_12' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_13' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_14' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_15' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_2' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_3' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_4' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_5' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_6' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_7' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_8' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 'up_es_9' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
|
|
INFO: [Common 17-14] Message 'IP_Flow 19-5107' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 'm_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '31:0' is present in all ports of the interface 's_axi'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
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|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
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|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
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WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
|
|
INFO: [Common 17-14] Message 'IP_Flow 19-5462' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '11:0' is present in all ports of the interface 'up_es_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_13'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_14'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_15'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_2'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_3'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_5'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_6'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_7'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_ch_9'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_12'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_4'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_cm_8'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_0'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_1'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
|
|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_10'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [IP_Flow 19-5151] The Range '15:0' is present in all ports of the interface 'up_es_11'. It is assumed that this is meant to declare an array of interface. If this is not the desired behaviour, switch of this feature by disabling the parameter 'ips.enableInterfaceArrayInference'.
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|
INFO: [Common 17-14] Message 'IP_Flow 19-5151' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
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|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
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|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_wdata' and definition port 'wdata'.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'm_axi_rdata' and definition port 'rdata'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'm_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_0': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_1': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_10': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_11': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_12': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_13': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_14': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_15': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_16': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_17': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_18': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_19': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_2': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_20': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_21': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_22': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_23': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_24': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_25': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_26': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_27': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_28': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_29': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_3': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_30': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_31': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_4': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_5': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_6': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_7': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_8': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "enb" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "addr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "wr" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 's_axi_9': A port map to the required logical port "ready" of the bus abstraction "analog.com:interface:if_xcvr_cm_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_ch_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_ch_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_cm_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_cm_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_0' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_0_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_10' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_10_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_11' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_11_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_12' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_12_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_13' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_13_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_14' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_14_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_15' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_15_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_1' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_1_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_2' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_2_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_3' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_3_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_4' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_4_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_5' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_5_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_6' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_6_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_7' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_7_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_8' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_8_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_0': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_1': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_10': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_11': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_2': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_3': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_4': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_5': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_6': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_7': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_8': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3480] slave: Portmap direction mismatched between component port 'up_es_addr_9' and definition port 'addr'.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "rd" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-1965] Bus Interface 'up_es_9_9': A port map to the required logical port "data" of the bus abstraction "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" is missing.
|
|
WARNING: [IP_Flow 19-3158] Bus Interface 'm_axi': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
|
|
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Synthesis'.
|
|
Resolution: Remove the file from the specified file group.
|
|
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file '../../scripts/adi_xilinx_device_info_enc.tcl' found in file group 'Simulation'.
|
|
Resolution: Remove the file from the specified file group.
|
|
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
|
|
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qkintexuplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qrkintexu. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qvirtexuplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplus. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family qzynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4623] Unrecognized family zynquplusRFSOC. Please verify spelling and reissue command to set the supported files.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
|
|
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
|
|
# adi_ip_infer_mm_interfaces axi_adxcvr
|
|
INFO: [IP_Flow 19-3166] Bus Interface 's_axi': References existing memory map 's_axi'.
|
|
INFO: [IP_Flow 19-3164] Bus Interface 'm_axi': References existing address space 'm_axi'.
|
|
# adi_init_bd_tcl
|
|
# adi_ip_bd axi_adxcvr "bd/bd.tcl"
|
|
# set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
|
|
# set_property master_address_space_ref m_axi \
|
|
# [ipx::get_bus_interfaces m_axi \
|
|
# -of_objects [ipx::current_core]]
|
|
# for {set n 0} {$n < 16} {incr n} {
|
|
#
|
|
# if {($n%4) == 0} {
|
|
# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \
|
|
# "enb up_cm_enb_${n} "\
|
|
# "addr up_cm_addr_${n} "\
|
|
# "wr up_cm_wr_${n} "\
|
|
# "wdata up_cm_wdata_${n} "\
|
|
# "rdata up_cm_rdata_${n} "\
|
|
# "ready up_cm_ready_${n} "]
|
|
# }
|
|
#
|
|
# adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \
|
|
# "enb up_es_enb_${n} "\
|
|
# "addr up_es_addr_${n} "\
|
|
# "wr up_es_wr_${n} "\
|
|
# "reset up_es_reset_${n} "\
|
|
# "wdata up_es_wdata_${n} "\
|
|
# "rdata up_es_rdata_${n} "\
|
|
# "ready up_es_ready_${n} "]
|
|
#
|
|
# adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \
|
|
# "pll_locked up_ch_pll_locked_${n} "\
|
|
# "rst up_ch_rst_${n} "\
|
|
# "user_ready up_ch_user_ready_${n} "\
|
|
# "rst_done up_ch_rst_done_${n} "\
|
|
# "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\
|
|
# "rate up_ch_rate_${n} "\
|
|
# "sys_clk_sel up_ch_sys_clk_sel_${n} "\
|
|
# "out_clk_sel up_ch_out_clk_sel_${n} "\
|
|
# "tx_diffctrl up_ch_tx_diffctrl_${n} "\
|
|
# "tx_postcursor up_ch_tx_postcursor_${n} "\
|
|
# "tx_precursor up_ch_tx_precursor_${n} "\
|
|
# "enb up_ch_enb_${n} "\
|
|
# "addr up_ch_addr_${n} "\
|
|
# "wr up_ch_wr_${n} "\
|
|
# "wdata up_ch_wdata_${n} "\
|
|
# "rdata up_ch_rdata_${n} "\
|
|
# "ready up_ch_ready_${n} "]
|
|
#
|
|
# }
|
|
# ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
|
|
# ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
|
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
|
|
# set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
|
# -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
|
|
# set_property enablement_dependency \
|
|
# {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \
|
|
# [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
|
|
# [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \
|
|
# [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \
|
|
# [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \
|
|
# [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \
|
|
# [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \
|
|
# [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \
|
|
# [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \
|
|
# [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \
|
|
# [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
|
|
# [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \
|
|
# [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \
|
|
# [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
|
|
# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
|
|
# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \
|
|
# [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \
|
|
# [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]]
|
|
# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \
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# [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \
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# [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \
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# [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \
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# [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
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# [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \
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# [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \
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# [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \
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# [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \
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# [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \
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# [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \
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# [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \
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# [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \
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# [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
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# [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \
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# [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \
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# [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \
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# [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \
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# [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \
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# [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \
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# [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]]
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# set_property enablement_dependency \
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# {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \
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# (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \
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# [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
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# set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \
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# [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]]
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# adi_add_auto_fpga_spec_params
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# ipx::create_xgui_files [ipx::current_core]
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# ipx::save_core [ipx::current_core]
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INFO: [Common 17-206] Exiting Vivado at Wed Dec 8 20:25:35 2021...
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