Archived
634 lines
15 KiB
Verilog
634 lines
15 KiB
Verilog
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2021/8/13 00:24:20
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// Design Name:
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// Module Name: LMX2595
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
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// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T)))
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//////////////////////////////////////////////////////////////////////////////////
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module adf4371_a(//20.375Ghz ~ 23.875Ghz
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input sysclk ,//40MHZ
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input arstn ,
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output cs ,
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input mux_out ,
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output sclk ,
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output sdio ,
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input [3:0] rf_en ,
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input SW_PLL ,
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input CAL_F ,
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input [3:0] ceshi_model ,
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input adf4371_hop ,
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output o_cfgover ,
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input[11:0] fre_code
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);
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localparam DATA_WIDTH = 24 ;
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localparam DATA_LENTH = 72 ;
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localparam WAIT_ld = 40000 ;
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//*****************************************************************************
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reg[7:0] cnt_word = 8'd0 ;
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reg csb_reg = 1'b1 ;
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reg[5:0] cnt_bits = 6'd0 ;
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reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ;
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reg[3:0] state = 4'b000 ;
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reg spi_sdo = 1'b0, spi_csb = 1'b1;
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wire pll_locked ;
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reg cfgover ;
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reg[31:0] cnt_lock = 32'd0 ;
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reg[31:0] cnt_locked = 32'd0 ;
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wire[15:0] band ;
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assign o_cfgover =cfgover ;
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//-----------------------------------
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assign pll_locked = mux_out ;
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assign sclk = spi_csb ? 1'b0 : ~sysclk ;
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assign cs = spi_csb & csb_reg ;
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assign sdio = spi_sdo ;
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//-----------------------------------
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wire [7:0] SI_BAND_SEL ; //VCO频段
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wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置
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reg[13:0] MOD2 ;
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reg[13:0] FRAC2 ;
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reg[24:0] FRAC1 ;
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reg[15:0] INT ;
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assign SI_BAND_SEL = band[15:8] ;
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assign SI_VCO_SEL_BIAS_CODE = band[7:0] ;
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reg[2:0] hop_en ;
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reg[15:0] code ;
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reg[11:0] pre_fre_code ;
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reg[3:0] rf_en_r ;
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reg[2:0] CAL_F_R ;
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reg [3:0] R_DIV ;
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reg [3:0] D ;
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wire[13:0] douta3 ;
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wire[13:0] douta4 ;
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wire[24:0] douta2 ;
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wire[15:0] douta1 ;
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//-----------------------------------
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INT_ROMb int_rom (
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.sysclk(sysclk),
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.addra(code),
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.douta(douta1)
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);
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// Instantiate the module
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FRAC1 frac1_rom (
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.clka(sysclk),
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.addra(code),
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.douta(douta2)
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);
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// FRAC1_ROM FRAC1_ROM (
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// .clka(sysclk), // input clka
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// .addra(code), // input [11 : 0] addra
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// .douta(douta2) // output [24 : 0] douta
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//);
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frac2_rom frac2_rom (
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.sysclk(sysclk),
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.addra(code),
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.douta(douta4)
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);
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mod2_rom mod2_rom (
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.sysclk(sysclk),
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.addra(code),
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.douta(douta3)
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);
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band_rom_a band_rom_a (
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.sysclk(sysclk),
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.addra(code),
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.douta(band) // output [15 : 0] douta
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);
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//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)
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INT<=douta1;
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else if(code==24 || code==26 )
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INT<=76;
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else if(code==424 )
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INT<=77;
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else if(code==426 )
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INT<=78;
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else if(code==824 || code==826 )
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INT<=79;
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else if(code==1224)
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INT<=80;
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else if(code==1226 )
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INT<=81;
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else if(code==1624 || code==1626 )
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INT<=82;
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else if(code==2024 )
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INT<=83;
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else if(code==2026 )
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INT<=84;
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else if(code==2424 || code==2426 )
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INT<=85;
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else if(code==2824 )
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INT<=86;
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else if( code==2826 )
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INT<=87;
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else
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INT<=douta1;
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end
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)
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FRAC1<=douta2;
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else if(code==24 )
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FRAC1<=16651386;
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else if(code==26 )
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FRAC1<=16903045;
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else if(code==424 )
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FRAC1<=33428602;
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else if(code==426 )
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FRAC1<=125829;
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else if(code==824 )
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FRAC1<=16651386;
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else if(code==826 )
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FRAC1<=16903045;
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else if(code==1224)
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FRAC1<=33428602;
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else if(code==1226 )
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FRAC1<=125829;
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else if(code==1624)
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FRAC1<=16651386;
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else if(code==1626 )
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FRAC1<=16903045;
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else if(code==2024 )
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FRAC1<=33428602;
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else if(code==2026 )
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FRAC1<=125829;
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else if(code==2424 )
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FRAC1<=16651386;
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else if(code==2426 )
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FRAC1<=16903045;
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else if(code==2824 )
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FRAC1<=33428602;
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else if( code==2826 )
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FRAC1<=125829;
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else
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FRAC1<=douta2;
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end
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)
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MOD2<=douta3;
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else if(code==24 )
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MOD2<=25;
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else if(code==26 )
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MOD2<=25;
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else if(code==424 )
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MOD2<=25;
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else if(code==426 )
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MOD2<=25;
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else if(code==824 )
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MOD2<=25;
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else if(code==826 )
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MOD2<=25;
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else if(code==1224)
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MOD2<=25;
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else if(code==1226 )
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MOD2<=25;
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else if(code==1624)
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MOD2<=25;
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else if(code==1626 )
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MOD2<=25;
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else if(code==2024 )
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MOD2<=25;
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else if(code==2026 )
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MOD2<=25;
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else if(code==2424 )
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MOD2<=25;
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else if(code==2426 )
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MOD2<=25;
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else if(code==2824 )
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MOD2<=25;
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else if( code==2826 )
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MOD2<=25;
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else
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MOD2<=douta3;
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end
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)
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FRAC2<=douta4;
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else if(code==24 )
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FRAC2<=22;
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else if(code==26 )
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FRAC2<=3;
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else if(code==424 )
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FRAC2<=22;
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else if(code==426 )
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FRAC2<=3;
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else if(code==824 )
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FRAC2<=22;
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else if(code==826 )
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FRAC2<=3;
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else if(code==1224)
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FRAC2<=22;
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else if(code==1226 )
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FRAC2<=3;
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else if(code==1624)
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FRAC2<=22;
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else if(code==1626 )
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FRAC2<=3;
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else if(code==2024 )
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FRAC2<=22;
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else if(code==2026 )
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FRAC2<=3;
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else if(code==2424 )
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FRAC2<=22;
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else if(code==2426 )
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FRAC2<=3;
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else if(code==2824 )
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FRAC2<=22;
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else if( code==2826 )
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FRAC2<=3;
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else
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FRAC2<=douta4;
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end
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)begin
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R_DIV<=4'b1;
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D<=4'b0;
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end
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else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 )
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begin
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R_DIV<= 4'd3;
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D<=4'd2;
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end
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else
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begin
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R_DIV<=4'b1;
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D<=4'b0;
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end
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end
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//----------------------------------------------------------------
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)
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pre_fre_code<=11'h6d6;
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else if(CAL_F_R==3'b011)
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pre_fre_code<=fre_code;
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else
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pre_fre_code<=pre_fre_code;
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end
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)
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code<=16'h0;
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else if(hop_en==2'b01)
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code<=fre_code;
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else
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code<=code;
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end
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)begin
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hop_en <= 3'b0;
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rf_en_r <= 4'b0;
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CAL_F_R <= 3'b0;
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end
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else begin
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hop_en <= {hop_en[1:0],adf4371_hop};
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CAL_F_R <= {CAL_F_R[1:0],CAL_F};
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rf_en_r <= rf_en ;
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end
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end
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)
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csb_reg <= 1'b1;
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else
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csb_reg <= spi_csb;
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end
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)
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cnt_locked<=32'b0;
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else if(cnt_locked==WAIT_ld)
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cnt_locked<=32'b0;
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else if(!pll_locked)
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cnt_locked<=cnt_locked+1'b1;
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else
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cnt_locked<=32'b0;
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end
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always@(posedge sysclk,negedge arstn)begin
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if(~arstn)begin
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cfgdata <= 0;
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cnt_word <= 7'd0;
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cnt_bits <= 6'd0;
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state <= 4'b0;
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cnt_lock <= 32'd0;
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spi_csb <= 1'b1;
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cfgover <= 1'b0;
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spi_sdo <= 1'b0;
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end
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else begin
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case(state)
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4'd0:begin
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cnt_word <= 7'd0;
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if(rf_en==1'b1)
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state <= 4'd0;
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else if(cnt_lock >= 32'd4000)
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state <= 4'd1;
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else
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state <= state;
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if(rf_en==1'b0)
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cnt_lock <= cnt_lock + 1'b1;
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else
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cnt_lock<=32'd0;
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end
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4'd1:begin
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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if(rf_en==1'b1)
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state <= 4'd0;
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else
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state <= 4'd2;
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end
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4'd2:begin
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cfgdata <= regdata;
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cnt_bits <= 6'd0;
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state <= 4'd3;
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end
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4'd3:begin
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spi_csb <= 1'b0;
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spi_sdo <= cfgdata[DATA_WIDTH-1];
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cfgdata <= cfgdata << 1'b1;
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cnt_bits <= cnt_bits + 1'b1;
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if(cnt_bits == DATA_WIDTH-1)begin
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state <= 4'd4;
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cnt_word <= cnt_word + 1'b1;
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end
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cnt_lock <= 32'd0;
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end
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4'd4:begin
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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cnt_lock <= 32'd0;
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cnt_bits <= 32'd0;
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if(cnt_word == DATA_LENTH)begin
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state <= 4'd5;
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end
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else
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state <= 4'd1;
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end
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4'd5:begin
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if(cnt_lock>=40000 || pll_locked)begin
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cnt_lock <= 32'd0 ;
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state <= 4'd6 ;
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end
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else begin
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cnt_lock <=cnt_lock+1'b1;
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state <= state ;
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end
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end
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4'd6:begin
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cnt_word <= 7'd0;
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if(pll_locked)
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state <= 4'd7 ;
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else
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state <= 4'b1 ;
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end
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//----------------------------------------------------------------
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4'd7:begin//IDLE
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cnt_word <= DATA_LENTH;
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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cnt_bits <= 6'd0;
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cfgover <= 1'b0;
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if(rf_en==4'b1)
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state <= state;
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else if(rf_en==4'b0 && rf_en_r==4'b1 )
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state <= 4'd0;
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else if(hop_en==2'b10 || cnt_locked==WAIT_ld )
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state <= 4'd8;
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else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
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state <= 4'd12;
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else
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state <= state;
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end
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4'd8:begin
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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state <= 4'd9;
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end
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4'd9:begin
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cfgdata <= regdata;
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cnt_bits <= 6'd0;
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state <= 4'd10;
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end
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4'd10:begin
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spi_csb <= 1'b0;
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spi_sdo <= cfgdata[DATA_WIDTH-1];
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cfgdata <= cfgdata << 1'b1;
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cnt_bits <= cnt_bits + 1'b1;
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if(cnt_bits == DATA_WIDTH-1)begin
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state <= 4'd11;
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cnt_word <= cnt_word + 1'b1;
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end
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end
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4'd11:begin
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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cnt_lock <= 32'd0;
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cnt_bits <= 32'd0;
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if(cnt_word == 8'd85)begin
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state <= 4'd7;
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end
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else
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state <= 4'd8;
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end
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4'd12:begin
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spi_csb <= 1'b1;
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spi_sdo <= 1'b0;
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state <= 4'd13;
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end
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4'd13:begin
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cnt_bits <= 6'd0;
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state <= 4'd14;
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if(ceshi_model==4'ha)
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cfgdata<={16'h0025,8'h13};
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else if(ceshi_model==4'hb)
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cfgdata<={16'h0025,8'h00};
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else if(SW_PLL)
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cfgdata<={16'h0025,8'h13};
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else
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cfgdata<={16'h0025,8'h00};
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end
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4'd14:begin
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spi_csb <= 1'b0;
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spi_sdo <= cfgdata[DATA_WIDTH-1];
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cfgdata <= cfgdata << 1'b1;
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cnt_bits <= cnt_bits + 1'b1;
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if(cnt_bits == DATA_WIDTH-1)begin
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state <= 4'd7;
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cfgover <= 1'b1;
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cnt_word <= cnt_word ;
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end
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end
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//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
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default: begin
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spi_csb <= 1'b1;
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state <= 4'd0;
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cnt_lock <= 32'd0;
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cnt_word <= 8'd0;
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end
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endcase
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end
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end
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always@(posedge sysclk,negedge arstn)
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begin
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if(!arstn)
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regdata <= {16'h0000,8'h18 };
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else case(cnt_word)
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8'd0 : regdata <= {16'h0000,8'h18 };
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8'd1 : regdata <= {16'h0001,8'h00 };
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8'd2 : regdata <= {16'h0003,8'h00 };
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8'd3 : regdata <= {16'h0004,8'h00 };
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8'd4 : regdata <= {16'h0005,8'h00 };
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8'd5 : regdata <= {16'h0006,8'hFF };
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8'd6 : regdata <= {16'h000C,8'h00 };
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8'd7 : regdata <= {16'h000D,8'h00 };
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8'd8 : regdata <= {16'h0010 ,INT[7:0] } ;
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8'd9 : regdata <= {16'h0011 ,INT[15:8] } ;
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8'd10 : regdata <= {16'h0012,8'h00 };//[6]No Autocalibration
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//8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration
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8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ;
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8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ;
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8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ;
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8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ;
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8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ;
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8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ;
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8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ;
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8'd18 : regdata <= {16'h001B,8'h00 };
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8'd19 : regdata <= {16'h001C,8'h00 };
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8'd20 : regdata <= {16'h001D,8'h00 };
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8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵
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// 8'd21 : regdata <= { 16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵
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||
8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
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||
8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld
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8'd24 : regdata <= {16'h0021,8'h00 };
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8'd25 : regdata <= {16'h0022,D,4'd0 };//[4]2分频 [5]double 2倍频器
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8'd26 : regdata <= {16'h0023,8'h00 };
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8'd27 : regdata <= {16'h0024,8'h80 };//Fout_clk DIV_SEL
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8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN
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||
8'd29 : regdata <= {16'h0026,8'h1F };
|
||
8'd30 : regdata <= {16'h0027,8'hCD };
|
||
//8'd30 : regdata <= {16'h0027,8'hCD };
|
||
8'd31 : regdata <= {16'h0028,8'h83 };
|
||
8'd32 : regdata <= {16'h002A,8'h00 };
|
||
8'd33 : regdata <= {16'h002B,8'h00 };
|
||
8'd34 : regdata <= {16'h002C,8'h44 };
|
||
8'd35 : regdata <= {16'h002D,8'h11 };
|
||
8'd36 : regdata <= {16'h002E,8'h12 };
|
||
8'd37 : regdata <= {16'h002F,8'h94 };
|
||
8'd38 : regdata <= {16'h0030,8'h2A };
|
||
8'd39 : regdata <= {16'h0031,8'h02 };
|
||
8'd40 : regdata <= {16'h0032,8'h04 };
|
||
8'd41 : regdata <= {16'h0033,8'h22 };
|
||
8'd42 : regdata <= {16'h0034,8'h25 };
|
||
8'd43 : regdata <= {16'h0035,8'hFA };
|
||
8'd44 : regdata <= {16'h0036,8'h30 };
|
||
8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段
|
||
8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置
|
||
8'd47 : regdata <= {16'h0039,8'h07 };
|
||
8'd48 : regdata <= {16'h003A,8'h55 };
|
||
8'd49 : regdata <= {16'h003D,8'h00 };
|
||
8'd50 : regdata <= {16'h003E,8'h0C };
|
||
8'd51 : regdata <= {16'h003F,8'h80 };
|
||
8'd52 : regdata <= {16'h0040,8'h50 };
|
||
8'd53 : regdata <= {16'h0041,8'h28 };
|
||
8'd54 : regdata <= {16'h0042,8'h00 };
|
||
8'd55 : regdata <= {16'h0043,8'h00 };
|
||
8'd56 : regdata <= {16'h0044,8'h00 };
|
||
8'd57 : regdata <= {16'h0045,8'h00 };
|
||
8'd58 : regdata <= {16'h0046,8'h00 };
|
||
8'd59 : regdata <= {16'h0047,8'hC0 };
|
||
8'd60 : regdata <= {16'h0052,8'hF4 };
|
||
8'd61 : regdata <= {16'h006C,8'h00 };
|
||
8'd62 : regdata <= {16'h006E,8'h00 };
|
||
8'd63 : regdata <= {16'h006F,8'h00 };
|
||
8'd64 : regdata <= {16'h0070,8'hE3 };
|
||
8'd65 : regdata <= {16'h0071,8'h60 };
|
||
8'd66 : regdata <= {16'h0072,8'h32 };
|
||
8'd67 : regdata <= {16'h0073,8'h00 };
|
||
8'd68 : regdata <= {16'h0079,8'h00 };
|
||
8'd69 : regdata <= {16'h007A,8'h00 };
|
||
8'd70 : regdata <= {16'h007B,8'h00 };
|
||
8'd71 : regdata <= {16'h007C,8'h00 };
|
||
|
||
//跳频
|
||
8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||
8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||
8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ;
|
||
8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ;
|
||
8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||
8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ;
|
||
8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ;
|
||
8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ;
|
||
8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ;
|
||
8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ;
|
||
8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ;
|
||
8'd83:regdata <= { 16'h0011 ,INT[15:8] } ;
|
||
8'd84:regdata <= { 16'h0010 ,INT[7:0] } ;
|
||
|
||
default: regdata <= regdata;
|
||
endcase
|
||
end
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
endmodule
|