Archived
151 lines
3.2 KiB
Verilog
151 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 20:42:39 09/29/2021
|
|
// Design Name:
|
|
// Module Name: spi_master
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
module spi_master #(parameter BIT_NUM = 95 )(
|
|
input i_clk ,
|
|
input debug_clk ,
|
|
input i_sys_rst_n ,
|
|
input i_spi_sck ,
|
|
input i_spi_cs ,
|
|
output o_spi_sdo ,
|
|
input i_spi_sdi ,
|
|
input i_LD_LO3 ,
|
|
input i_LD1 ,
|
|
input i_LD2 ,
|
|
input[3:0] i_cal1_mgc ,
|
|
input[3:0] i_cal2_mgc ,
|
|
input[3:0] i_cal3_mgc ,
|
|
input[3:0] i_cal4_mgc ,
|
|
input[7:0] i_temp ,
|
|
input[31:0] i_frame_count
|
|
|
|
);
|
|
|
|
wire [BIT_NUM:0] data ;
|
|
reg [BIT_NUM:0] data_r ;
|
|
reg [BIT_NUM:0] data_reg ;
|
|
assign data={ 8'hAA ,
|
|
i_temp ,
|
|
7'b0,i_LD_LO3 ,
|
|
7'b0,i_LD1 ,
|
|
7'b0,i_LD2 ,
|
|
i_cal1_mgc,i_cal2_mgc ,
|
|
i_cal3_mgc,i_cal4_mgc ,
|
|
i_frame_count ,
|
|
8'hCC } ;
|
|
|
|
wire spi_sck ;
|
|
wire spi_cs ;
|
|
reg spi_sdo ;
|
|
reg [2:0] reg_cs ;
|
|
reg [31:0] cnt ;
|
|
|
|
assign spi_sck = i_spi_sck;
|
|
assign spi_cs = i_spi_cs;
|
|
assign o_spi_sdo = spi_sdo;
|
|
|
|
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)
|
|
reg_cs<=3'b111;
|
|
else
|
|
reg_cs<={reg_cs[1:0],i_spi_cs};
|
|
end
|
|
|
|
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)
|
|
data_r<={8'hAA,80'b0,8'hCC};
|
|
else if(reg_cs[2:1]==2'b10)
|
|
data_r<={8'hAA,data[87:8],8'hCC};
|
|
end
|
|
|
|
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)
|
|
spi_sdo <= 1'b0 ;
|
|
else if(!spi_cs)
|
|
spi_sdo <= data_r[cnt];
|
|
else
|
|
spi_sdo <= 1'b0 ;
|
|
end
|
|
|
|
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)
|
|
cnt<=BIT_NUM;
|
|
else if(spi_cs==1 | cnt==0)
|
|
cnt<=BIT_NUM;
|
|
else
|
|
cnt<=cnt-1;
|
|
end
|
|
|
|
//------------debug------------
|
|
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
|
if(!i_sys_rst_n)
|
|
data_reg <= 0 ;
|
|
else if(!spi_cs)
|
|
data_reg <= {data_reg,spi_sdo} ;
|
|
else
|
|
data_reg <= data_reg ;
|
|
end
|
|
//------------debug------------
|
|
|
|
/*
|
|
wire [40:0] SYNC_OUT ;
|
|
wire [35:0] CONTROL0 ;
|
|
wire [35:0] CONTROL1 ;
|
|
wire [150:0] TRIG0 ;
|
|
|
|
vio u_vio (
|
|
.CONTROL (CONTROL0), // INOUT BUS [35:0]
|
|
.CLK (i_clk), // IN
|
|
.SYNC_OUT (SYNC_OUT) // OUT BUS [33:0]
|
|
);
|
|
|
|
|
|
icon u_icon (
|
|
.CONTROL0 (CONTROL0), // INOUT BUS [35:0]
|
|
.CONTROL1 (CONTROL1) // INOUT BUS [35:0]
|
|
);
|
|
|
|
|
|
ila u_ila (
|
|
.CONTROL (CONTROL1), // INOUT BUS [35:0]
|
|
.CLK (debug_clk), // IN
|
|
.TRIG0 (TRIG0) // IN BUS [39:0]
|
|
);
|
|
|
|
|
|
assign TRIG0[0] = i_LD_LO3;
|
|
assign TRIG0[1] = i_LD1 ;
|
|
assign TRIG0[2] = i_LD2 ;
|
|
assign TRIG0[98:3] = data_r ;
|
|
assign TRIG0[101:99] = reg_cs ;
|
|
assign TRIG0[132:102] = cnt ;
|
|
assign TRIG0[133] = i_spi_sck ;
|
|
assign TRIG0[134] = i_spi_cs ;
|
|
assign TRIG0[135] = o_spi_sdo ;
|
|
assign TRIG0[136] = i_spi_sdi ;
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
|
|
endmodule
|