Archived
619 lines
16 KiB
Verilog
619 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_cmos_if #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter CLK_DESKEW = 0,
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parameter USE_SSI_CLK = 1,
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parameter DELAY_REFCLK_FREQUENCY = 200) (
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// physical interface (receive)
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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// physical interface (transmit)
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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// ensm control
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output enable,
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output txnrx,
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// clock (common to both receive and transmit)
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input rst,
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input clk,
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output l_clk,
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// receive data path interface
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output adc_valid,
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output [47:0] adc_data,
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output adc_status,
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input adc_r1_mode,
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input adc_ddr_edgesel,
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// transmit data path interface
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input dac_valid,
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input [47:0] dac_data,
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input dac_clksel,
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input dac_r1_mode,
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// tdd interface
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input tdd_enable,
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input tdd_txnrx,
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input tdd_mode,
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// delay interface
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input mmcm_rst,
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input up_clk,
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input up_rstn,
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input up_enable,
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input up_txnrx,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input [15:0] up_dac_dld,
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input [79:0] up_dac_dwdata,
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output [79:0] up_dac_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked,
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// drp interface
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked);
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// internal registers
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reg adc_r1_mode_n = 'd0;
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reg rx_r1_mode = 'd0;
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reg rx_locked_m1 = 'd0;
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reg rx_locked = 'd0;
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reg [ 1:0] rx_frame = 'd0;
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reg [11:0] rx_data_1 = 'd0;
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reg adc_valid_p = 'd0;
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reg [47:0] adc_data_p = 'd0;
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reg adc_status_p = 'd0;
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reg adc_valid_n = 'd0;
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reg [47:0] adc_data_n = 'd0;
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reg adc_status_n = 'd0;
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reg adc_valid_int = 'd0;
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reg [47:0] adc_data_int = 'd0;
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reg adc_status_int = 'd0;
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reg [ 1:0] tx_clk_p = 'd0;
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reg [ 1:0] tx_frame_p = 'd0;
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reg [11:0] tx_data_0_p = 'd0;
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reg [11:0] tx_data_1_p = 'd0;
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reg [ 1:0] tx_clk_n = 'd0;
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reg [ 1:0] tx_frame_n = 'd0;
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reg [11:0] tx_data_0_n = 'd0;
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reg [11:0] tx_data_1_n = 'd0;
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reg [ 1:0] tx_clk = 'd0;
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reg [ 1:0] tx_frame = 'd0;
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reg [11:0] tx_data_0 = 'd0;
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reg [11:0] tx_data_1 = 'd0;
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reg up_enable_int = 'd0;
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reg up_txnrx_int = 'd0;
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reg enable_up_m1 = 'd0;
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reg txnrx_up_m1 = 'd0;
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reg enable_up = 'd0;
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reg txnrx_up = 'd0;
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reg enable_int = 'd0;
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reg txnrx_int = 'd0;
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reg enable_int_p = 'd0;
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reg txnrx_int_p = 'd0;
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// internal signals
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wire [11:0] rx_data_1_s;
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wire [11:0] rx_data_0_s;
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wire [ 1:0] rx_frame_s;
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wire locked_s;
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// drp interface signals
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assign up_drp_rdata = 32'd0;
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assign up_drp_ready = 1'd0;
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assign up_drp_locked = 1'd1;
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// r1mode
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generate if (CLK_DESKEW) begin
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reg adc_r1_mode_n = 'd0;
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always @(negedge clk) begin
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adc_r1_mode_n <= adc_r1_mode;
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end
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always @(posedge l_clk) begin
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rx_r1_mode <= adc_r1_mode_n;
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end
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end else begin /* CLK_DESKEW == 0 */
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always @(posedge l_clk) begin
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rx_r1_mode <= adc_r1_mode;
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end
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end
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endgenerate
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// adc-status
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assign delay_locked = locked_s;
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always @(posedge l_clk) begin
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rx_locked_m1 <= locked_s;
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rx_locked <= rx_locked_m1;
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end
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// frame check
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always @(posedge l_clk) begin
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if (rx_r1_mode == 1'd1) begin
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rx_frame <= rx_frame_s;
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end else begin
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rx_frame <= ~rx_frame_s;
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end
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end
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// data hold
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always @(posedge l_clk) begin
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rx_data_1 <= rx_data_1_s;
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end
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// delineation
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always @(posedge l_clk) begin
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case ({rx_r1_mode, rx_frame_s})
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3'b011: begin
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adc_valid_p <= 1'b0;
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adc_data_p[47:24] <= 24'd0;
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adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
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end
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3'b000: begin
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adc_valid_p <= 1'b1;
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adc_data_p[47:24] <= {rx_data_1_s, rx_data_0_s};
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adc_data_p[23: 0] <= adc_data_p[23:0];
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end
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3'b001: begin
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adc_valid_p <= 1'b0;
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adc_data_p[47:24] <= 24'd0;
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adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
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end
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3'b010: begin
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adc_valid_p <= 1'b1;
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adc_data_p[47:24] <= {rx_data_0_s, rx_data_1};
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adc_data_p[23: 0] <= adc_data_p[23:0];
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end
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3'b110: begin
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adc_valid_p <= 1'b1;
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adc_data_p[47:24] <= 24'd0;
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adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
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end
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3'b101: begin
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adc_valid_p <= 1'b1;
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adc_data_p[47:24] <= 24'd0;
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adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
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end
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default: begin
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adc_valid_p <= 1'b0;
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adc_data_p <= 48'd0;
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end
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endcase
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end
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// adc-status
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always @(posedge l_clk) begin
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if (rx_frame == rx_frame_s) begin
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adc_status_p <= rx_locked;
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end else begin
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adc_status_p <= 1'b0;
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end
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end
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// transfer to common clock
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generate if (CLK_DESKEW) begin
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reg adc_valid_n = 'd0;
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reg [47:0] adc_data_n = 'd0;
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reg adc_status_n = 'd0;
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always @(negedge l_clk) begin
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adc_valid_n <= adc_valid_p;
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adc_data_n <= adc_data_p;
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adc_status_n <= adc_status_p;
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end
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always @(posedge clk) begin
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adc_valid_int <= adc_valid_n;
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adc_data_int <= adc_data_n;
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adc_status_int <= adc_status_n;
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end
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assign adc_valid = adc_valid_int;
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assign adc_data = adc_data_int;
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assign adc_status = adc_status_int;
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end else begin /* CLK_DESKEW == 0 */
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always @(posedge clk) begin
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adc_valid_int <= adc_valid_p;
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adc_data_int <= adc_data_p;
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adc_status_int <= adc_status_p;
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end
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assign adc_valid = adc_valid_int;
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assign adc_data = adc_data_int;
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assign adc_status = adc_status_int;
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end
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endgenerate
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// dac-tx interface
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always @(posedge clk) begin
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tx_clk_p <= {~dac_clksel, dac_clksel};
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end
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always @(posedge clk) begin
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case ({dac_r1_mode, dac_valid})
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3'b00: begin
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tx_frame_p <= 2'b00;
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tx_data_0_p <= dac_data[35:24];
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tx_data_1_p <= dac_data[47:36];
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end
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2'b01: begin
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tx_frame_p <= 2'b11;
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tx_data_0_p <= dac_data[11:0];
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tx_data_1_p <= dac_data[23:12];
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end
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2'b11: begin
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tx_frame_p <= 2'b01;
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tx_data_0_p <= dac_data[11:0];
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tx_data_1_p <= dac_data[23:12];
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end
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default: begin
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tx_frame_p <= 2'd0;
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tx_data_0_p <= 12'd0;
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tx_data_1_p <= 12'd0;
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end
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endcase
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end
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// transfer to local clock
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generate if (CLK_DESKEW) begin
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reg [ 1:0] tx_clk_n = 'd0;
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reg tx_frame_n = 'd0;
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reg [ 5:0] tx_data_0_n = 'd0;
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reg [ 5:0] tx_data_1_n = 'd0;
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always @(negedge clk) begin
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tx_clk_n <= tx_clk_p;
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tx_frame_n <= tx_frame_p;
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tx_data_0_n <= tx_data_0_p;
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tx_data_1_n <= tx_data_1_p;
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end
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always @(posedge l_clk) begin
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tx_clk <= tx_clk_n;
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tx_frame <= tx_frame_n;
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tx_data_0 <= tx_data_0_n;
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tx_data_1 <= tx_data_1_n;
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end
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end else begin /* CLK_DESKEW == 0 */
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always @(posedge l_clk) begin
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tx_clk <= tx_clk_p;
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tx_frame <= tx_frame_p;
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tx_data_0 <= tx_data_0_p;
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tx_data_1 <= tx_data_1_p;
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end
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end
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endgenerate
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// tdd/ensm control
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always @(posedge up_clk) begin
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up_enable_int <= up_enable;
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up_txnrx_int <= up_txnrx;
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end
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always @(posedge clk or posedge rst) begin
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if (rst == 1'b1) begin
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enable_up_m1 <= 1'b0;
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txnrx_up_m1 <= 1'b0;
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enable_up <= 1'b0;
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txnrx_up <= 1'b0;
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end else begin
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enable_up_m1 <= up_enable_int;
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txnrx_up_m1 <= up_txnrx_int;
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enable_up <= enable_up_m1;
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txnrx_up <= txnrx_up_m1;
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end
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end
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always @(posedge clk) begin
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if (tdd_mode == 1'b1) begin
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enable_int <= tdd_enable;
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txnrx_int <= tdd_txnrx;
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end else begin
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enable_int <= enable_up;
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txnrx_int <= txnrx_up;
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end
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end
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generate if (CLK_DESKEW) begin
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reg enable_int_n = 'd0;
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reg txnrx_int_n = 'd0;
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always @(negedge clk) begin
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enable_int_n <= enable_int;
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txnrx_int_n <= txnrx_int;
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end
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always @(posedge l_clk) begin
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enable_int_p <= enable_int_n;
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txnrx_int_p <= txnrx_int_n;
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end
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end else begin /* CLK_DESKEW == 0 */
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always @(posedge l_clk) begin
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enable_int_p <= enable_int;
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txnrx_int_p <= txnrx_int;
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end
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end
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endgenerate
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// receive data interface, ibuf -> idelay -> iddr
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genvar i;
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generate
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for (i = 0; i < 12; i = i + 1) begin: g_rx_data
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ad_data_in #(
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.SINGLE_ENDED (1),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_rx_data (
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.rx_clk (l_clk),
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.rx_data_in_p (rx_data_in[i]),
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.rx_data_in_n (1'd0),
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.rx_data_p (rx_data_1_s[i]),
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.rx_data_n (rx_data_0_s[i]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[i]),
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.up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
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.up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// receive frame interface, ibuf -> idelay -> iddr
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ad_data_in #(
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.SINGLE_ENDED (1),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_rx_frame (
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.rx_clk (l_clk),
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.rx_data_in_p (rx_frame_in),
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.rx_data_in_n (1'd0),
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.rx_data_p (rx_frame_s[1]),
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.rx_data_n (rx_frame_s[0]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[12]),
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.up_dwdata (up_adc_dwdata[64:60]),
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.up_drdata (up_adc_drdata[64:60]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (locked_s));
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// transmit data interface, oddr -> obuf
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generate
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for (i = 0; i < 12; i = i + 1) begin: g_tx_data
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ad_data_out #(
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.SINGLE_ENDED (1),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_tx_data (
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.tx_clk (l_clk),
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.tx_data_p (tx_data_1[i]),
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.tx_data_n (tx_data_0[i]),
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.tx_data_out_p (tx_data_out[i]),
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.tx_data_out_n (),
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.up_clk (up_clk),
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.up_dld (up_dac_dld[i]),
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.up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
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.up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
|
|
.delay_locked ());
|
|
end
|
|
endgenerate
|
|
|
|
// transmit frame interface, oddr -> obuf
|
|
|
|
ad_data_out #(
|
|
.SINGLE_ENDED (1),
|
|
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
|
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
|
.IODELAY_CTRL (0),
|
|
.IODELAY_GROUP (IO_DELAY_GROUP),
|
|
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
|
i_tx_frame (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (tx_frame[1]),
|
|
.tx_data_n (tx_frame[0]),
|
|
.tx_data_out_p (tx_frame_out),
|
|
.tx_data_out_n (),
|
|
.up_clk (up_clk),
|
|
.up_dld (up_dac_dld[12]),
|
|
.up_dwdata (up_dac_dwdata[64:60]),
|
|
.up_drdata (up_dac_drdata[64:60]),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_locked ());
|
|
|
|
// transmit clock interface, oddr -> obuf
|
|
|
|
ad_data_out #(
|
|
.SINGLE_ENDED (1),
|
|
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
|
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
|
.IODELAY_CTRL (0),
|
|
.IODELAY_GROUP (IO_DELAY_GROUP),
|
|
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
|
i_tx_clk (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (tx_clk[1]),
|
|
.tx_data_n (tx_clk[0]),
|
|
.tx_data_out_p (tx_clk_out),
|
|
.tx_data_out_n (),
|
|
.up_clk (up_clk),
|
|
.up_dld (up_dac_dld[13]),
|
|
.up_dwdata (up_dac_dwdata[69:65]),
|
|
.up_drdata (up_dac_drdata[69:65]),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_locked ());
|
|
|
|
// enable, oddr -> obuf
|
|
|
|
ad_data_out #(
|
|
.SINGLE_ENDED (1),
|
|
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
|
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
|
.IODELAY_CTRL (0),
|
|
.IODELAY_GROUP (IO_DELAY_GROUP),
|
|
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
|
i_enable (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (enable_int_p),
|
|
.tx_data_n (enable_int_p),
|
|
.tx_data_out_p (enable),
|
|
.tx_data_out_n (),
|
|
.up_clk (up_clk),
|
|
.up_dld (up_dac_dld[14]),
|
|
.up_dwdata (up_dac_dwdata[74:70]),
|
|
.up_drdata (up_dac_drdata[74:70]),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_locked ());
|
|
|
|
// txnrx, oddr -> obuf
|
|
|
|
ad_data_out #(
|
|
.SINGLE_ENDED (1),
|
|
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
|
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
|
.IODELAY_CTRL (0),
|
|
.IODELAY_GROUP (IO_DELAY_GROUP),
|
|
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
|
i_txnrx (
|
|
.tx_clk (l_clk),
|
|
.tx_data_p (txnrx_int_p),
|
|
.tx_data_n (txnrx_int_p),
|
|
.tx_data_out_p (txnrx),
|
|
.tx_data_out_n (),
|
|
.up_clk (up_clk),
|
|
.up_dld (up_dac_dld[15]),
|
|
.up_dwdata (up_dac_dwdata[79:75]),
|
|
.up_drdata (up_dac_drdata[79:75]),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_locked ());
|
|
|
|
// device clock interface (receive clock)
|
|
|
|
generate if (USE_SSI_CLK == 1) begin
|
|
ad_data_clk #(
|
|
.SINGLE_ENDED (1))
|
|
i_clk (
|
|
.rst (1'd0),
|
|
.locked (),
|
|
.clk_in_p (rx_clk_in),
|
|
.clk_in_n (1'd0),
|
|
.clk (l_clk));
|
|
end else begin
|
|
assign l_clk = clk;
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|