Archived
146 lines
4.6 KiB
Verilog
146 lines
4.6 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_up_sysref #(
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parameter DATA_PATH_WIDTH = 2
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) (
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input up_clk,
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input up_reset,
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input core_clk,
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input [11:0] up_raddr,
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output reg [31:0] up_rdata,
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input up_wreq,
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input [11:0] up_waddr,
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input [31:0] up_wdata,
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input up_cfg_is_writeable,
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output reg up_cfg_sysref_oneshot,
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output reg [7:0] up_cfg_lmfc_offset,
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output reg up_cfg_sysref_disable,
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input core_event_sysref_alignment_error,
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input core_event_sysref_edge
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);
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reg [1:0] up_sysref_status;
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reg [1:0] up_sysref_status_clear;
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wire [1:0] up_sysref_event;
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sync_event #(
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.NUM_OF_EVENTS(2)
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) i_cdc_sysref_event (
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.in_clk(core_clk),
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.in_event({
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core_event_sysref_alignment_error,
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core_event_sysref_edge
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}),
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.out_clk(up_clk),
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.out_event(up_sysref_event)
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);
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always @(posedge up_clk) begin
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if (up_reset == 1'b1) begin
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up_sysref_status <= 2'b00;
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end else begin
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up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event;
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end
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end
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always @(*) begin
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case (up_raddr)
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/* JESD SYSREF configuraton */
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12'h040: up_rdata = {
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/* 02-31 */ 30'h00, /* Reserved for future use */
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/* 01 */ up_cfg_sysref_oneshot,
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/* 00 */ up_cfg_sysref_disable
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};
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12'h041: up_rdata = {
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/* 10-31 */ 22'h00, /* Reserved for future use */
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/* 02-09 */ up_cfg_lmfc_offset,
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/* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */
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};
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12'h042: up_rdata = {
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/* 02-31 */ 30'h00,
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/* 00-01 */ up_sysref_status
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};
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default: up_rdata = 32'h00000000;
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endcase
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end
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always @(posedge up_clk) begin
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if (up_reset == 1'b1) begin
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up_cfg_sysref_oneshot <= 1'b0;
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up_cfg_lmfc_offset <= 'h00;
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up_cfg_sysref_disable <= 1'b0;
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end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
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case (up_waddr)
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/* JESD SYSREF configuraton */
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12'h040: begin
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up_cfg_sysref_oneshot <= up_wdata[1];
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up_cfg_sysref_disable <= up_wdata[0];
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end
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12'h041: begin
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/* Aligned to data path width */
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up_cfg_lmfc_offset <= up_wdata[9:DATA_PATH_WIDTH];
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end
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endcase
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end
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end
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always @(*) begin
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if (up_wreq == 1'b1 && up_waddr == 12'h042) begin
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up_sysref_status_clear = up_wdata[1:0];
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end else begin
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up_sysref_status_clear = 2'b00;
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end
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end
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endmodule
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