Archived
josh
cd256a8cd6
gitignore structure is updated to work with single and multi project situation under a single project directory
100 lines
4.4 KiB
Tcl
100 lines
4.4 KiB
Tcl
#LVDS
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set_property PACKAGE_PIN AJ13 [get_ports DARY]
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set_property IOSTANDARD LVTTL [get_ports Din1]
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set_property IOSTANDARD LVTTL [get_ports Dout1]
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set_property IOSTANDARD LVTTL [get_ports Din2]
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set_property IOSTANDARD LVTTL [get_ports Dout2]
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set_property IOSTANDARD LVTTL [get_ports PW_DOWN]
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set_property IOSTANDARD LVTTL [get_ports TR]
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set_property PACKAGE_PIN AF14 [get_ports DCLK_in]
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set_property PACKAGE_PIN AG17 [get_ports DCLK_out]
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set_property PACKAGE_PIN AA13 [get_ports Din1]
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set_property PACKAGE_PIN AK12 [get_ports Din2]
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set_property PACKAGE_PIN AK16 [get_ports Dout1]
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set_property PACKAGE_PIN AK15 [get_ports Dout2]
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set_property PACKAGE_PIN AF15 [get_ports PW_DOWN]
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set_property PACKAGE_PIN AJ18 [get_ports TR]
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set_property IOSTANDARD LVTTL [get_ports DARY]
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set_property IOSTANDARD LVTTL [get_ports DCLK_out]
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set_property IOSTANDARD LVTTL [get_ports DCLK_in]
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set_property PACKAGE_PIN AE22 [get_ports CLK_25M]
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set_property IOSTANDARD LVTTL [get_ports CLK_25M]
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#GLINK
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set_property PACKAGE_PIN AD10 [get_ports glink_refclk_p]
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set_property PACKAGE_PIN AD9 [get_ports glink_refclk_n]
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set_property PACKAGE_PIN AH9 [get_ports rx_datain_n_ch_a]
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set_property PACKAGE_PIN AH10 [get_ports rx_datain_p_ch_a]
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set_property PACKAGE_PIN AK9 [get_ports tx_dataout_n_ch_a]
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set_property PACKAGE_PIN AK10 [get_ports tx_dataout_p_ch_a]
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set_property PACKAGE_PIN AJ7 [get_ports rx_datain_n_ch_b]
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set_property PACKAGE_PIN AJ8 [get_ports rx_datain_p_ch_b]
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set_property PACKAGE_PIN AK5 [get_ports tx_dataout_n_ch_b]
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set_property PACKAGE_PIN AK6 [get_ports tx_dataout_p_ch_b]
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#BEAM
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set_property PACKAGE_PIN Y25 [get_ports {SEL1_TR[0]}]
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set_property PACKAGE_PIN Y30 [get_ports {SEL1_TR[1]}]
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set_property PACKAGE_PIN AA30 [get_ports {SEL1_TR[2]}]
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set_property PACKAGE_PIN AB29 [get_ports {SEL1_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SEL1_TR*]
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set_property PACKAGE_PIN AC29 [get_ports {SEL2_TR[0]}]
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set_property PACKAGE_PIN AD29 [get_ports {SEL2_TR[1]}]
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set_property PACKAGE_PIN AD25 [get_ports {SEL2_TR[2]}]
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set_property PACKAGE_PIN AE26 [get_ports {SEL2_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SEL2_TR*]
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set_property PACKAGE_PIN AG29 [get_ports {SEL3_TR[0]}]
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set_property PACKAGE_PIN AF30 [get_ports {SEL3_TR[1]}]
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set_property PACKAGE_PIN AG30 [get_ports {SEL3_TR[2]}]
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set_property PACKAGE_PIN AG26 [get_ports {SEL3_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SEL3_TR*]
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set_property PACKAGE_PIN U21 [get_ports {SEL4_TR[0]}]
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set_property PACKAGE_PIN P30 [get_ports {SEL4_TR[1]}]
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set_property PACKAGE_PIN R30 [get_ports {SEL4_TR[2]}]
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set_property PACKAGE_PIN T30 [get_ports {SEL4_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SEL4_TR*]
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set_property PACKAGE_PIN AA29 [get_ports {CLK_TR[0]}]
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set_property PACKAGE_PIN AF28 [get_ports {CLK_TR[1]}]
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set_property PACKAGE_PIN AJ30 [get_ports {CLK_TR[2]}]
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set_property PACKAGE_PIN T29 [get_ports {CLK_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports CLK_TR*]
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set_property PACKAGE_PIN Y27 [get_ports {TR_TR[0]}]
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set_property PACKAGE_PIN AD28 [get_ports {TR_TR[1]}]
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set_property PACKAGE_PIN AH28 [get_ports {TR_TR[2]}]
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set_property PACKAGE_PIN N29 [get_ports {TR_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports TR_TR*]
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set_property PACKAGE_PIN AA27 [get_ports {DATA_TR[0]}]
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set_property PACKAGE_PIN AE27 [get_ports {DATA_TR[1]}]
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set_property PACKAGE_PIN AK30 [get_ports {DATA_TR[2]}]
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set_property PACKAGE_PIN U29 [get_ports {DATA_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports DATA_TR*]
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set_property PACKAGE_PIN Y28 [get_ports {SYN_TR[0]}]
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set_property PACKAGE_PIN AE28 [get_ports {SYN_TR[1]}]
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set_property PACKAGE_PIN AH29 [get_ports {SYN_TR[2]}]
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set_property PACKAGE_PIN P29 [get_ports {SYN_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SYN_TR*]
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set_property PACKAGE_PIN AB30 [get_ports {SEL_TR[0]}]
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set_property PACKAGE_PIN AB27 [get_ports {SEL_TR[1]}]
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set_property PACKAGE_PIN AG27 [get_ports {SEL_TR[2]}]
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set_property PACKAGE_PIN U30 [get_ports {SEL_TR[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SEL_TR*]
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set_property PACKAGE_PIN AB25 [get_ports R_DLY]
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set_property PACKAGE_PIN AC26 [get_ports T_DLY]
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set_property IOSTANDARD LVCMOS33 [get_ports R_DLY]
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set_property IOSTANDARD LVCMOS33 [get_ports T_DLY]
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create_clock -period 40.000 -name CLK_25M -waveform {0.000 20.000} -add [get_ports CLK_25M]
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create_clock -period 8.000 -name glink_refclk_p -waveform {0.000 4.000} [get_nets glink_refclk_p]
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#set false path |