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josh
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326 lines
8.3 KiB
Verilog
326 lines
8.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08/06/2022 04:29:04 PM
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// Design Name:
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// Module Name: c2c_bridge
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module c2c_bridge
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#(
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parameter [31:0] FRAME_HEAD = 31'h7E7E7E7E,
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parameter [31:0] FRAME_MAX_LENGTH = 32'h00002000
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)
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(
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input clk , // input clk, 100Mhz
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input rst , // input rst, active high
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//interface data
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input c2c_clkin ,
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output c2c_clkout,
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input c2c_din ,
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output c2c_dout ,
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// bram interface
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output tx_bram_clk , // output bram clk
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output [31:0] tx_bram_addr , // output bram address[31:0]
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input [31:0] tx_bram_dout , // input bram data[31:0]
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output reg tx_bram_en , // output bram enable, active-high
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output reg [3:0] tx_bram_we , // output bram write enable, active-high
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output rx_bram_clk , // output bram clk
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output reg [31:0] rx_bram_addr , // output bram address[31:0]
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output reg [31:0] rx_bram_din , // output bram data[31:0]
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output reg rx_bram_en , // output bram enable, active-high
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output reg [3:0] rx_bram_we , // output bram write enable, active-high
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// pl interrupt
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output reg pl_rd_done , // output pl_rd_done, active-high
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output reg pl_wr_done , // output pl_wr_done, active-high
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// flag signal from ps to pl
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input ps_rd_done , // input ps_rd_done, active-high
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input ps_wr_done // input ps_wr_done, active-high
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);
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reg [31:0] c2c_in_32;
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reg [39:0] tx_bitcnt;
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reg [39:0] rx_bitcnt;
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reg [31:0] tx_frame_length;//byte
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reg [31:0] rx_frame_length;//byte
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always @ ( posedge c2c_clkin or posedge rst) begin
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if ( rst ) begin
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c2c_in_32 <= 32'h00000000;
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end
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else begin
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c2c_in_32 <= {c2c_in_32[30:0],c2c_din};
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end
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end
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reg [31:0] c2c_out_32;
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always @ ( posedge clk or posedge rst) begin
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if ( rst ) begin
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c2c_out_32 <= 32'h00000000;
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end
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else if(tx_bitcnt[4:0] == 5'd1) begin
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c2c_out_32 <= tx_bram_dout;
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end
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else begin
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c2c_out_32 <= {c2c_out_32[30:0],1'b0};
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end
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end
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assign c2c_dout = c2c_out_32[31];
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// dly
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wire pl_read_start;
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reg ps_rd_done_d0;
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reg ps_rd_done_d1;
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reg ps_rd_done_d2;
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reg ps_wr_done_d0;
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reg ps_wr_done_d1;
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reg ps_wr_done_d2;
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always @ ( posedge clk ) begin
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if ( rst ) begin
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ps_rd_done_d0 <= 1'b0;
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ps_rd_done_d1 <= 1'b0;
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ps_rd_done_d2 <= 1'b0;
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ps_wr_done_d0 <= 1'b0;
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ps_wr_done_d1 <= 1'b0;
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ps_wr_done_d2 <= 1'b0;
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end else begin
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ps_rd_done_d0 <= ps_rd_done;
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ps_rd_done_d1 <= ps_rd_done_d0;
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ps_rd_done_d2 <= ps_rd_done_d1;
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ps_wr_done_d0 <= ps_wr_done;
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ps_wr_done_d1 <= ps_wr_done_d0;
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ps_wr_done_d2 <= ps_wr_done_d1;
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end
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end
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assign pl_read_start = ps_wr_done_d1 ^ ps_wr_done_d2;
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////////////////// TX PORT /////////////////////
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// state machine
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reg [3:0] tx_state_next;
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reg [3:0] tx_state;
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localparam S_TX_WAIT = 4'd0;
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localparam S_TX_PLREAD = 4'd1;
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always @ (*) begin
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case (tx_state)
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S_TX_WAIT : begin
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if ( pl_read_start ) begin //can read
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tx_state_next <= S_TX_PLREAD;
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end
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else begin
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tx_state_next <= S_TX_WAIT;
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end
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end
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S_TX_PLREAD : begin // read bram
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if(tx_bram_addr[31:0] >= tx_frame_length[31:0]) begin//frame end
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tx_state_next <= S_TX_WAIT;
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end
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else if(tx_bram_addr > FRAME_MAX_LENGTH)begin //overtime
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tx_state_next <= S_TX_WAIT;
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end
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else begin
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tx_state_next <= S_TX_PLREAD;
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end
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end
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default : begin
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tx_state_next <= S_TX_WAIT;
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end
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endcase
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end
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always @(posedge clk) begin
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tx_state <= tx_state_next;
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end
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//tx_bitcnt
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always @(posedge clk) begin
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if(rst) begin
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tx_bitcnt[39:0] <= 40'd0;
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end
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else if(tx_state == S_TX_PLREAD) begin
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tx_bitcnt[39:0] <= tx_bitcnt[39:0]+40'd1;
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end
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else begin
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tx_bitcnt[39:0] <= 40'd0;
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end
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end
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//tx_frame_length
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always @(posedge clk) begin
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if(rst) begin
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tx_frame_length[31:0] <= 32'hFFFFFFFF;
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end
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else if(tx_bitcnt == 40'h0000000021) begin
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tx_frame_length[31:0] <= tx_bram_dout;
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end
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else if(tx_state == S_TX_PLREAD) begin
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tx_frame_length[31:0] <= tx_frame_length[31:0];
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end
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else begin
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tx_frame_length[31:0] <= 32'hFFFFFFFF;
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end
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end
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// tx_bram_en
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// always enable
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always @(posedge clk) begin
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tx_bram_en <= 1'b1;
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end
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// tx_bram_we
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// always disable
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always @(posedge clk) begin
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tx_bram_we[3:0] <= 4'h0;
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end
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//tx_bram_addr
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assign tx_bram_addr = {tx_bitcnt[34:5],2'b0};
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assign c2c_clkout = clk;
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assign tx_bram_clk = clk;
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////////////////// RX PORT /////////////////////
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reg [3:0] rx_state_next;
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reg [3:0] rx_state;
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localparam S_RX_WAIT = 4'd0;
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localparam S_RX_PLWRITE = 4'd1;
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always @ (*) begin
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case (rx_state)
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S_TX_WAIT : begin
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if ( c2c_in_32 == FRAME_HEAD ) begin //can write
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rx_state_next <= S_RX_PLWRITE;
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end
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else begin
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rx_state_next <= S_RX_WAIT;
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end
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end
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S_RX_PLWRITE : begin // write bram
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if(rx_bram_addr[31:0] >= rx_frame_length[31:0]) begin//frame end
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rx_state_next <= S_RX_WAIT;
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end
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else if(rx_bram_addr > FRAME_MAX_LENGTH)begin //overtime
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rx_state_next <= S_RX_WAIT;
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end
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else begin
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rx_state_next <= S_RX_PLWRITE;
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end
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end
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default : begin
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rx_state_next <= S_RX_WAIT;
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end
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endcase
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end
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always @(posedge c2c_clkin) begin
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rx_state <= rx_state_next;
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end
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//tx_bitcnt
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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rx_bitcnt[39:0] <= 40'd0;
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end
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else if(rx_state == S_RX_PLWRITE) begin
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rx_bitcnt[39:0] <= rx_bitcnt[39:0] + 40'd1;
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end
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else begin
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rx_bitcnt <= 40'd0;
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end
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end
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//rx_frame_length
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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rx_frame_length[31:0] <= 32'hFFFFFFFF;
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end
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else if(rx_bitcnt == 40'h000000001F) begin
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rx_frame_length[31:0] <= c2c_in_32;
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end
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else if(rx_state == S_RX_PLWRITE) begin
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rx_frame_length[31:0] <= rx_frame_length[31:0];
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end
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else begin
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rx_frame_length[31:0] <= 32'hFFFFFFFF;
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end
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end
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// rx_bram_en
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// always enable
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always @(posedge c2c_clkin) begin
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rx_bram_en <= 1'b1;
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end
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// rx_bram_we
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// always disable
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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rx_bram_we[3:0] <= 4'h0;
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end
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else if(rx_state_next == S_RX_PLWRITE) begin
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rx_bram_we[3:0] <= 4'hF;
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end
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else begin
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rx_bram_we[3:0] <= 4'h0;
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end
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end
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//rx_bram_addr
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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rx_bram_addr[31:0] <= 32'd0;
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end
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else if(rx_state == S_RX_PLWRITE) begin
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rx_bram_addr = {rx_bitcnt[34:5],2'b0} + 32'd4;
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end
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else begin
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rx_bram_addr[31:0] <= 32'b0;
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end
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end
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reg [7:0] pl_wr_done_cnt;
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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pl_wr_done_cnt <= 8'd0;
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pl_wr_done <= 1'b0;
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end
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else if(rx_state == S_RX_PLWRITE
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&& rx_state_next == S_RX_WAIT
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&& rx_bram_addr <= FRAME_MAX_LENGTH) begin
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pl_wr_done_cnt <= 8'd16;
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pl_wr_done <= 1'b1;
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end
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else if(pl_wr_done_cnt > 0) begin
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pl_wr_done_cnt <= pl_wr_done_cnt - 8'd1;
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pl_wr_done <= 1'b1;
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end
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else begin
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pl_wr_done_cnt <= 8'd0;
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pl_wr_done <= 1'b0;
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end
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end
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always @(posedge c2c_clkin or posedge rst) begin
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if(rst) begin
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rx_bram_din[31:0] <= 32'd0;
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end
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else begin
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rx_bram_din <= c2c_in_32;
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end
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end
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assign rx_bram_clk = c2c_clkin;
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endmodule
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