Archived
josh
cd256a8cd6
gitignore structure is updated to work with single and multi project situation under a single project directory
50 lines
2.0 KiB
Verilog
50 lines
2.0 KiB
Verilog
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
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// Date : Mon Sep 12 16:54:54 2022
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// Host : Ksling-PC running 64-bit major release (build 9200)
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// Command : write_verilog -mode synth_stub ttop_S_005X.v
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// Design : ttop_S
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z045ffg900-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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module ttop_S_005X(clock100, clkdv, clk50, n_rst, LED0, LED1, CLK, DATA, EN,
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DARY, TR, CLK_TR, DATA_TR, SYN_TR, SEL_TR, SEL4_TR, SEL3_TR, SEL2_TR, SEL1_TR, TR_TR, T_DLY, R_DLY, test1,
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test2, test3, test4, test5, test6, test7, test8)
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/* synthesis syn_black_box black_box_pad_pin="clock100,clkdv,clk50,n_rst,LED0,LED1,CLK,DATA,EN,DARY,TR,CLK_TR[3:0],DATA_TR[3:0],SYN_TR[3:0],SEL_TR[3:0],SEL4_TR[3:0],SEL3_TR[3:0],SEL2_TR[3:0],SEL1_TR[3:0],TR_TR[3:0],T_DLY,R_DLY,test1,test2,test3,test4,test5,test6,test7,test8" */;
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input clock100;
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input clkdv;
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input clk50;
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input n_rst;
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output LED0;
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output LED1;
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input CLK;
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input DATA;
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input EN;
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input DARY;
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input TR;
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output [3:0]CLK_TR;
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output [3:0]DATA_TR;
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output [3:0]SYN_TR;
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output [3:0]SEL_TR;
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output [3:0]SEL4_TR;
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output [3:0]SEL3_TR;
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output [3:0]SEL2_TR;
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output [3:0]SEL1_TR;
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output [3:0]TR_TR;
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output T_DLY;
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output R_DLY;
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output test1;
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output test2;
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output test3;
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output test4;
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output test5;
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output test6;
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output test7;
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output test8;
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endmodule
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