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josh
cd256a8cd6
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77 lines
2.0 KiB
Verilog
77 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/02/23 11:13:17
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// Design Name:
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// Module Name: sim_c2c_dma
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sim_c2c_dma(
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);
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//*************************Parameter Declarations******************************
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parameter CLK_PERIOD = 10.41666667;
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reg clk;
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initial begin
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clk = 1'b1;
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end
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always
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#(CLK_PERIOD/2) clk = !clk;
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reg rst;
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initial begin
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rst = 1'b1;
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#(CLK_PERIOD*10)
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rst = 1'b0;
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end
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reg [31:0] c2c_tx_fifo_tdata = 32'd0;
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always
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#(CLK_PERIOD) c2c_tx_fifo_tdata = c2c_tx_fifo_tdata + 32'd1;
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reg [191:0]c2c_din = 192'hFFFFFFFF_7E7E7E7E_10000207_12345678_9ABCDEFF_FFFFFFFF;
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always
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#(CLK_PERIOD) c2c_din[191:0] = {c2c_din[190:0],1'b0};
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c2c_bridge_dma u_c2c_bridge_dma(
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.clk (clk ), // input clk, 96Mhz
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.rst (rst ), // input rst, active high
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//interface data
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.c2c_clkin (clk ),
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.c2c_clkout ( ),
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.c2c_din (c2c_din[191] ),
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.c2c_dout ( ),
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//dma fifo interface
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.c2c_tx_fifo_tdata (c2c_tx_fifo_tdata ),
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.c2c_tx_fifo_tlast (1'b1 ),
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.c2c_tx_fifo_tready ( ),
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.c2c_tx_fifo_tvalid (1'b1 ),
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.c2c_rx_fifo_tdata ( ),
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.c2c_rx_fifo_tlast ( ),
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.c2c_rx_fifo_tready (1'b1 ),
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.c2c_rx_fifo_tvalid ( )
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);
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endmodule
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