Archived
271 lines
8.1 KiB
Verilog
271 lines
8.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_usb_fx3_if (
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input dma_rdy,
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input dma_wmk,
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input [ 3:0] fifo_rdy,
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input pclk,
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input reset_n,
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inout [31:0] data,
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output reg [ 1:0] addr,
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output reg slcs_n,
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output reg slrd_n,
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output reg sloe_n,
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output reg slwr_n,
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output reg pktend_n,
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output epswitch_n,
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input [ 4:0] fifo_num,
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input [10:0] fifo_direction,
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input trig,
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output reg [10:0] fifo_ready,
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output reg fx32dma_valid,
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input fx32dma_ready,
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output reg [31:0] fx32dma_data,
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output reg fx32dma_sop,
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input fx32dma_eop,
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input eot_fx32dma,
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output reg dma2fx3_ready,
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input dma2fx3_valid,
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input [31:0] dma2fx3_data,
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input dma2fx3_eop);
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// internal registers
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reg [ 3:0] state_gpif_ii = 4'h0;
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reg [ 3:0] next_state_gpif_ii = 4'h0;
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reg current_direction = 0;
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reg current_fifo = 0;
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reg slcs_n_d1 = 0;
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reg slcs_n_d2 = 0;
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reg slcs_n_d3 = 0;
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reg slcs_n_d4 = 0;
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reg slrd_n_d1 = 0;
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reg slrd_n_d2 = 0;
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reg slrd_n_d3 = 0;
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reg sloe_n_d1 = 0;
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reg pip = 0;
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localparam IDLE = 4'b0001;
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localparam READ_START = 4'b0010;
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localparam READ_DATA = 4'b0100;
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localparam WRITE_DATA = 4'b1000;
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assign data = (state_gpif_ii == WRITE_DATA && dma2fx3_valid && current_fifo) ? dma2fx3_data : 32'hz;
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assign epswitch_n = 1'b1;
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always @(fifo_num, fifo_rdy, fifo_direction) begin
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case(fifo_num)
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5'h0: begin
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current_direction = fifo_direction[0];
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current_fifo = fifo_rdy[0];
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end
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5'h1: begin
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current_direction = fifo_direction[1];
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current_fifo = fifo_rdy[1];
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end
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5'h2: begin
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current_direction = fifo_direction[2];
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current_fifo = fifo_rdy[2];
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end
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5'h3: begin
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current_direction = fifo_direction[3];
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current_fifo = fifo_rdy[3];
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end
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5'h4: begin
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current_direction = fifo_direction[4];
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current_fifo = fifo_rdy[0];
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end
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5'h5: begin
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current_direction = fifo_direction[5];
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current_fifo = fifo_rdy[0];
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end
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5'h6: begin
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current_direction = fifo_direction[6];
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current_fifo = fifo_rdy[0];
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end
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5'h7: begin
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current_direction = fifo_direction[7];
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current_fifo = fifo_rdy[0];
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end
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5'h8: begin
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current_direction = fifo_direction[8];
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current_fifo = fifo_rdy[0];
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end
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5'h9: begin
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current_direction = fifo_direction[9];
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current_fifo = fifo_rdy[0];
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end
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default: begin
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current_direction = 0;
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current_fifo = fifo_rdy[0];
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end
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endcase
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end
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// STATE MACHINE GPIF II
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always @(posedge pclk) begin
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if (reset_n == 1'b0 || trig == 1'b0 ) begin
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state_gpif_ii <= IDLE;
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end else begin
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state_gpif_ii <= next_state_gpif_ii;
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end
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end
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always @(*) begin
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case(state_gpif_ii)
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IDLE:
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if(trig == 1'b1 && current_fifo == 1'b1) begin
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if (current_direction == 0) begin
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next_state_gpif_ii = READ_START;
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end else begin
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next_state_gpif_ii = WRITE_DATA;
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end
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end else begin
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next_state_gpif_ii = IDLE;
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end
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READ_START:
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next_state_gpif_ii = READ_DATA;
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READ_DATA:
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if (eot_fx32dma == 1'b1) begin
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next_state_gpif_ii = IDLE;
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end else begin
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next_state_gpif_ii = READ_DATA;
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end
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WRITE_DATA:
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if(dma2fx3_eop == 1'b1) begin
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next_state_gpif_ii = IDLE;
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end else begin
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next_state_gpif_ii = WRITE_DATA;
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end
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default: next_state_gpif_ii = IDLE;
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endcase
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end
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always @(*) begin
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case(state_gpif_ii)
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IDLE: begin
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slcs_n = 1'b1;
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sloe_n = 1'b1;
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slrd_n = 1'b1;
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fx32dma_valid = 1'b0;
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fx32dma_sop = 1'b0;
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fx32dma_data = 32'h0;
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slwr_n = 1'b1;
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pktend_n = 1'b1;
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dma2fx3_ready = 1'b0;
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end
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READ_START: begin
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slcs_n = 1'b0;
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sloe_n = 1'b0;
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slrd_n = 1'b1;
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fx32dma_valid = 1'b0;
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fx32dma_sop = 1'b0;
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fx32dma_data = 32'h0;
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slwr_n = 1'b1;
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pktend_n = 1'b1;
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dma2fx3_ready = 1'b0;
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end
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READ_DATA: begin
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slcs_n = 1'b0;
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sloe_n = 1'b0;
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slrd_n = !fx32dma_ready | fx32dma_eop;
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fx32dma_valid = !slcs_n_d4 & !slrd_n_d3;
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fx32dma_sop = !slcs_n_d4 & !slrd_n_d3 & pip;
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fx32dma_data = data;
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slwr_n = 1'b1;
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pktend_n = 1'b1;
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dma2fx3_ready = 1'b0;
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end
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WRITE_DATA: begin
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slcs_n = 1'b0;
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sloe_n = 1'b1;
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slrd_n = 1'b1;
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fx32dma_valid = 1'b0;
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fx32dma_sop = 1'b0;
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fx32dma_data = 32'h0;
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slwr_n = !dma2fx3_valid | !current_fifo;
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dma2fx3_ready = current_fifo;
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pktend_n = !dma2fx3_eop;
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end
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default: begin
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slcs_n = 1'b1;
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sloe_n = 1'b1;
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slrd_n = 1'b1;
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fx32dma_valid = 1'b0;
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fx32dma_sop = 1'b0;
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fx32dma_data = 32'h0;
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slwr_n = 1'b1;
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pktend_n = 1'b1;
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dma2fx3_ready = 1'b0;
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end
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endcase
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end
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always @(posedge pclk) begin
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fifo_ready <= {7'h0,fifo_rdy};
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slrd_n_d1 <= slrd_n;
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slrd_n_d2 <= slrd_n_d1;
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slrd_n_d3 <= slrd_n_d2;
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slcs_n_d1 <= slcs_n;
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slcs_n_d2 <= slcs_n_d1;
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slcs_n_d3 <= slcs_n_d2;
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slcs_n_d4 <= slcs_n_d3;
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addr <= fifo_num[1:0];
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if (state_gpif_ii == IDLE) begin
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pip <= 1'b1;
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end else begin
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if (fx32dma_sop == 1'b1) begin
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pip <= 1'b0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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