Archived
659 lines
32 KiB
XML
659 lines
32 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>axi_jesd204_common</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
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<spirit:displayName>Synthesis</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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<spirit:modelName>jesd204_up_common</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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|
<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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|
<spirit:value>20a384cb</spirit:value>
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|
</spirit:parameter>
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|
</spirit:parameters>
|
|
</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>Verilog</spirit:language>
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|
<spirit:modelName>jesd204_up_common</spirit:modelName>
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|
<spirit:fileSetRef>
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|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:fileSetRef>
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|
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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|
</spirit:fileSetRef>
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|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>46282bf1</spirit:value>
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|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
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|
<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>fb8a8194</spirit:value>
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|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
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|
</spirit:views>
|
|
<spirit:ports>
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<spirit:port>
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<spirit:name>up_clk</spirit:name>
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<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ext_resetn</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>up_reset</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>up_reset_synchronizer</spirit:name>
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|
<spirit:wire>
|
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<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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|
<spirit:port>
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<spirit:name>core_clk</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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</spirit:wire>
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|
</spirit:port>
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<spirit:port>
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<spirit:name>core_reset_ext</spirit:name>
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<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
</spirit:wire>
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|
</spirit:port>
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|
<spirit:port>
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<spirit:name>core_reset</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>up_raddr</spirit:name>
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<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
|
|
</spirit:port>
|
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<spirit:port>
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<spirit:name>up_rdata</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
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<spirit:port>
|
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<spirit:name>up_wreq</spirit:name>
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<spirit:wire>
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|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
|
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</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_waddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_wdata</spirit:name>
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|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">31</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_extra_cfg</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXTRA_CFG_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_irq_trigger</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_IRQS')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>irq</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_cfg_is_writeable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_lanes_disable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_links_disable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_LINKS')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_beats_per_multiframe</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_octets_per_frame</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">7</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_disable_scrambler</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_cfg_disable_char_replacement</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>core_extra_cfg</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.EXTRA_CFG_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>reg</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
<spirit:name>PCORE_VERSION</spirit:name>
|
|
<spirit:displayName>Pcore Version</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCORE_VERSION">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>PCORE_MAGIC</spirit:name>
|
|
<spirit:displayName>Pcore Magic</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PCORE_MAGIC">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>ID</spirit:name>
|
|
<spirit:displayName>Id</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ID">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_LANES</spirit:name>
|
|
<spirit:displayName>Num Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LANES">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_LINKS</spirit:name>
|
|
<spirit:displayName>Num Links</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_LINKS">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>DATA_PATH_WIDTH</spirit:name>
|
|
<spirit:displayName>Data Path Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_PATH_WIDTH">2</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>MAX_OCTETS_PER_FRAME</spirit:name>
|
|
<spirit:displayName>Max Octets Per Frame</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MAX_OCTETS_PER_FRAME">256</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>NUM_IRQS</spirit:name>
|
|
<spirit:displayName>Num Irqs</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_IRQS">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>EXTRA_CFG_WIDTH</spirit:name>
|
|
<spirit:displayName>Extra Cfg Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXTRA_CFG_WIDTH">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>LINK_MODE</spirit:name>
|
|
<spirit:displayName>Link Mode</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.LINK_MODE">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>ENABLE_LINK_STATS</spirit:name>
|
|
<spirit:displayName>Enable Link Stats</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ENABLE_LINK_STATS">0</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>jesd204_up_common.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>jesd204_up_sysref.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../xilinx/common/up_clock_mon_constr.xdc</spirit:name>
|
|
<spirit:userFileType>xdc</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../common/up_clock_mon.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_ec760b7c</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0">
|
|
<xilinx:mode xilinx:name="copy_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>jesd204_up_common.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>jesd204_up_sysref.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>../../common/up_clock_mon.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0">
|
|
<xilinx:mode xilinx:name="copy_mode"/>
|
|
</xilinx:componentRef>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/jesd204_up_common_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_fb8a8194</spirit:userFileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:name>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:subCoreRef>
|
|
<xilinx:componentRef xilinx:vendor="analog.com" xilinx:library="user" xilinx:name="util_cdc" xilinx:version="1.0"/>
|
|
</xilinx:subCoreRef>
|
|
</spirit:vendorExtensions>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>ADI AXI JESD204B Common Library</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>PCORE_VERSION</spirit:name>
|
|
<spirit:displayName>Pcore Version</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCORE_VERSION">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>PCORE_MAGIC</spirit:name>
|
|
<spirit:displayName>Pcore Magic</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCORE_MAGIC">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ID</spirit:name>
|
|
<spirit:displayName>Id</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_LANES</spirit:name>
|
|
<spirit:displayName>Num Lanes</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LANES">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_LINKS</spirit:name>
|
|
<spirit:displayName>Num Links</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_LINKS">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>DATA_PATH_WIDTH</spirit:name>
|
|
<spirit:displayName>Data Path Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_PATH_WIDTH">2</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>MAX_OCTETS_PER_FRAME</spirit:name>
|
|
<spirit:displayName>Max Octets Per Frame</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MAX_OCTETS_PER_FRAME">256</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>NUM_IRQS</spirit:name>
|
|
<spirit:displayName>Num Irqs</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_IRQS">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>EXTRA_CFG_WIDTH</spirit:name>
|
|
<spirit:displayName>Extra Cfg Width</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.EXTRA_CFG_WIDTH">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LINK_MODE</spirit:name>
|
|
<spirit:displayName>Link Mode</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LINK_MODE">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ENABLE_LINK_STATS</spirit:name>
|
|
<spirit:displayName>Enable Link Stats</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_LINK_STATS">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">jesd204_up_common_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">azynquplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintexu</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qkintexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qrkintexu</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qvirtexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qzynquplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">qzynquplusRFSOC</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
|
<xilinx:family xilinx:lifeCycle="Production">zynquplusRFSOC</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>ADI AXI JESD204B Common Library</xilinx:displayName>
|
|
<xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
|
|
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
|
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
|
|
<xilinx:coreRevision>1</xilinx:coreRevision>
|
|
<xilinx:coreCreationDateTime>2021-12-08T12:24:39Z</xilinx:coreCreationDateTime>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7e19a25c"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="5a7b7604"/>
|
|
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="eea761fd"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1bc6769c"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|