Archived
73 lines
1.2 KiB
Verilog
73 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 15:35:03 01/27/2022
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// Design Name:
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// Module Name: mod2_rom
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module frac2_rom(
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input sysclk,
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input [11 : 0] addra,
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output reg[13:0] douta
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);
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reg[11:0] addr=0;
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always@(posedge sysclk)begin
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addr<=addra%25;
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end
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always@(posedge sysclk)begin
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case(addr)
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0 : douta <= 0;
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1 : douta <= 2;
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2 : douta <= 4;
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3 : douta <= 6;
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4 : douta <= 8;
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5 : douta <= 2;
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6 : douta <= 12;
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7 : douta <= 14;
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8 : douta <= 16;
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9 : douta <= 18;
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10 : douta <= 4;
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11 : douta <= 22;
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12 : douta <= 24;
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13 : douta <= 1;
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14 : douta <= 3;
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15 : douta <= 1;
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16 : douta <= 7;
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17 : douta <= 9;
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18 : douta <= 11;
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19 : douta <= 13;
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20 : douta <= 3;
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21 : douta <= 17;
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22 : douta <= 19;
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23 : douta <= 21;
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24 : douta <= 23;
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default:douta <= douta ;
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endcase
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end
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endmodule
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