Archived
119 lines
2.6 KiB
Verilog
119 lines
2.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 15:23:58 10/12/2020
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// Design Name: spi发送模块
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// Module Name: spi
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spi_tx #(parameter WHITH=32)(
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input clk,//系统时钟
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input rstn,//异步复位
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input tx_en,//发送使能
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input [WHITH-1:0] data_in,//待发送数据
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output reg spi_cs, //片选
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output reg spi_sclk, //同步时钟，等于clk/2
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output reg spi_sdo, //发送数据的线
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output reg DARY
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);
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//localparam [1:0] polaeity = 2'b10;//negedge 数据下降沿保持
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localparam [1:0] polaeity = 2'b01;//posedge 数据上降沿保持
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reg [2:0] state ; //状态机
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reg [WHITH-1:0] reg_data;//移位寄存器
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reg [5:0] cnt;//计数器，必须大于数据位宽
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wire CPOL ; //时钟空闲时电平
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wire CPHA ; //极性
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assign CPOL = polaeity[0] ;
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assign CPHA = polaeity[1] ;
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always @(posedge clk,negedge rstn)begin
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if(!rstn)begin
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state <= 3'd0;
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spi_cs <= 1'b1;
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spi_sclk <= CPOL;
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reg_data <= 1'd0;
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cnt <= 5'b0;
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spi_sdo <= 1'b0;
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DARY <= 1'b1;
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end
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else begin
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case(state)
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3'd0:begin//空闲态
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spi_sclk <= CPOL ;
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spi_cs <= 1'b1 ;
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spi_sdo <= 1'b0 ;
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DARY <= 1'b1 ;
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cnt <= 5'b0 ;
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reg_data <= data_in ;
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if(tx_en)//发送使能跳下一个状态
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state <= 3'd1 ;
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else
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state <= state ;
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end
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3'd1:begin
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spi_cs <= 1'b0 ;
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state <= 3'd2 ;
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reg_data <= data_in ;
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end
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3'd2:begin//数据移位态
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spi_cs <= 1'b0 ;
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reg_data <= reg_data<<1'b1 ;
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spi_sdo <= reg_data[WHITH-1] ;
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spi_sclk <= CPHA ;
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state <= (cnt >= WHITH-1) ? 3'd4:3'd3;
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end
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3'd3:begin//时钟翻转
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cnt <= cnt+1'b1 ;
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spi_sclk <= ~CPHA ;
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state <= 3'd2 ;
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end
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3'd4:begin//结束态
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state <= 3'd5;
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spi_sclk <= ~CPHA;
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end
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3'd5:begin//结束态
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state <= 3'd6;
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DARY <= 0;
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spi_sdo <= 1'b0 ;
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spi_cs <= 1'b1 ;
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end
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3'd6:begin//结束态
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state <= 3'd7;
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DARY <= 1;
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spi_cs <= 1'b1 ;
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end
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3'd7:begin//结束态
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state <= 3'd8;
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DARY <= 0;
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end
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3'd8:begin//结束态
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state <= 3'd0;
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DARY <= 1;
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end
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default :state<=3'd0;
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endcase
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end
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end
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endmodule
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