Archived
336 lines
10 KiB
Verilog
336 lines
10 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module axi_jesd204_rx #(
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parameter ID = 0,
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter ENABLE_LINK_STATS = 0
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) (
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [13:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [13:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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output irq,
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input core_clk,
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input core_reset_ext,
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output core_reset,
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output [NUM_LANES-1:0] core_cfg_lanes_disable,
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output [NUM_LINKS-1:0] core_cfg_links_disable,
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output [7:0] core_cfg_beats_per_multiframe,
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output [7:0] core_cfg_octets_per_frame,
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output core_cfg_disable_scrambler,
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output core_cfg_disable_char_replacement,
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output [7:0] core_cfg_lmfc_offset,
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output core_cfg_sysref_oneshot,
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output core_cfg_sysref_disable,
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output core_cfg_buffer_early_release,
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output [7:0] core_cfg_buffer_delay,
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output [7:0] core_cfg_frame_align_err_threshold,
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input [NUM_LANES-1:0] core_ilas_config_valid,
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input [2*NUM_LANES-1:0] core_ilas_config_addr,
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input [32*NUM_LANES-1:0] core_ilas_config_data,
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input core_event_sysref_alignment_error,
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input core_event_sysref_edge,
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input core_event_frame_alignment_error,
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input core_event_unexpected_lane_state_error,
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output [6:0] core_ctrl_err_statistics_mask,
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output core_ctrl_err_statistics_reset,
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input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
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input [1:0] core_status_ctrl_state,
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input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
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input [3*NUM_LANES-1:0] core_status_lane_emb_state,
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input [NUM_LANES-1:0] core_status_lane_ifs_ready,
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input [14*NUM_LANES-1:0] core_status_lane_latency,
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input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt
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);
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localparam PCORE_VERSION = 32'h00010461; // 1.04.a
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localparam PCORE_MAGIC = 32'h32303452; // 204R
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localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 3 : 2;
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/* Register interface signals */
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reg [31:0] up_rdata = 'h0;
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg up_rreq_d1 = 1'b0;
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wire up_wreq;
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wire up_rreq;
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wire [31:0] up_wdata;
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wire [11:0] up_waddr;
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wire [11:0] up_raddr;
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wire [31:0] up_rdata_common;
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wire [31:0] up_rdata_sysref;
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wire [31:0] up_rdata_rx;
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wire [4:0] up_irq_trigger;
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wire up_cfg_is_writeable;
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wire up_cfg_sysref_oneshot;
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wire up_cfg_sysref_disable;
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wire up_cfg_buffer_early_release;
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wire [7:0] up_cfg_buffer_delay;
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wire [7:0] up_cfg_lmfc_offset;
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wire [7:0] up_cfg_frame_align_err_threshold;
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wire up_reset;
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wire up_reset_synchronizer;
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wire up_event_frame_alignment_error;
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wire up_event_unexpected_lane_state_error;
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sync_event #(
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.NUM_OF_EVENTS (2)
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) i_sync_frame_align_err (
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.in_clk(core_clk),
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.in_event({core_event_unexpected_lane_state_error,
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core_event_frame_alignment_error}),
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.out_clk(s_axi_aclk),
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.out_event({up_event_unexpected_lane_state_error,
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up_event_frame_alignment_error})
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);
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assign up_irq_trigger = {3'b0,
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up_event_unexpected_lane_state_error,
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up_event_frame_alignment_error} &
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{5{~up_cfg_is_writeable}};
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up_axi #(
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.AXI_ADDRESS_WIDTH (14)
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) i_up_axi (
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.up_rstn(~up_reset),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_wack(up_wack),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata),
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.up_rack(up_rack)
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);
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jesd204_up_common #(
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.PCORE_VERSION(PCORE_VERSION),
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.PCORE_MAGIC(PCORE_MAGIC),
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.ID(ID),
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.NUM_IRQS(5),
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.EXTRA_CFG_WIDTH(27),
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.LINK_MODE(LINK_MODE),
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.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
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) i_up_common (
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.up_clk(s_axi_aclk),
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.ext_resetn(s_axi_aresetn),
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.up_reset(up_reset),
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.up_reset_synchronizer(up_reset_synchronizer),
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.core_clk(core_clk),
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.core_reset_ext(core_reset_ext),
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.core_reset(core_reset),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata_common),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_cfg_is_writeable(up_cfg_is_writeable),
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.up_irq_trigger(up_irq_trigger),
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.irq(irq),
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.core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe),
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.core_cfg_octets_per_frame(core_cfg_octets_per_frame),
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.core_cfg_lanes_disable(core_cfg_lanes_disable),
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.core_cfg_links_disable(core_cfg_links_disable),
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.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
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.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
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.up_extra_cfg({
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/* 19-26 */ up_cfg_frame_align_err_threshold,
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/* 18 */ up_cfg_sysref_disable,
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/* 17 */ up_cfg_sysref_oneshot,
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/* 16 */ up_cfg_buffer_early_release,
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/* 08-15 */ up_cfg_buffer_delay,
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/* 00-07 */ up_cfg_lmfc_offset
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}),
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.core_extra_cfg({
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/* 19-26 */ core_cfg_frame_align_err_threshold,
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/* 18 */ core_cfg_sysref_disable,
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/* 17 */ core_cfg_sysref_oneshot,
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/* 16 */ core_cfg_buffer_early_release,
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/* 08-15 */ core_cfg_buffer_delay,
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/* 00-07 */ core_cfg_lmfc_offset
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})
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);
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jesd204_up_sysref #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_up_sysref (
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.up_clk(s_axi_aclk),
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.up_reset(up_reset),
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.core_clk(core_clk),
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.core_event_sysref_edge(core_event_sysref_edge),
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.core_event_sysref_alignment_error(core_event_sysref_alignment_error),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata_sysref),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_cfg_is_writeable(up_cfg_is_writeable),
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.up_cfg_lmfc_offset(up_cfg_lmfc_offset),
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.up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
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.up_cfg_sysref_disable(up_cfg_sysref_disable)
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);
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jesd204_up_rx #(
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.NUM_LANES(NUM_LANES),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_up_rx (
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.up_clk(s_axi_aclk),
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.up_reset(up_reset),
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.up_reset_synchronizer(up_reset_synchronizer),
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.core_clk(core_clk),
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.core_reset(core_reset),
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.up_rreq(up_rreq),
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.up_raddr(up_raddr),
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.up_rdata(up_rdata_rx),
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.up_wreq(up_wreq),
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.up_waddr(up_waddr),
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.up_wdata(up_wdata),
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.up_cfg_is_writeable(up_cfg_is_writeable),
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.up_cfg_buffer_early_release(up_cfg_buffer_early_release),
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.up_cfg_buffer_delay(up_cfg_buffer_delay),
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.up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
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.core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
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.core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
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.core_status_ctrl_state(core_status_ctrl_state),
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.core_status_lane_cgs_state(core_status_lane_cgs_state),
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.core_status_lane_emb_state(core_status_lane_emb_state),
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.core_status_lane_ifs_ready(core_status_lane_ifs_ready),
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.core_status_lane_latency(core_status_lane_latency),
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.core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
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.core_status_err_statistics_cnt(core_status_err_statistics_cnt),
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.core_ilas_config_valid(core_ilas_config_valid),
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.core_ilas_config_addr(core_ilas_config_addr),
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.core_ilas_config_data(core_ilas_config_data)
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);
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always @(posedge s_axi_aclk) begin
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up_wack <= up_wreq;
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// ILAS memory takes one clock cycle before the data is ready, hence the extra
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// delay.
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up_rreq_d1 <= up_rreq;
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up_rack <= up_rreq_d1;
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if (up_rreq_d1 == 1'b1) begin
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up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
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end
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end
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endmodule
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