Archived
132 lines
5.0 KiB
Verilog
132 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module pack_interconnect #(
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parameter PORT_DATA_WIDTH = 16,
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parameter PORT_ADDRESS_WIDTH = 3,
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parameter MUX_ORDER = 2,
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parameter NUM_STAGES = 2,
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parameter PACK = 0 // 0 = Unpack, 1 = Pack
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) (
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input [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl,
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input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in,
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output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out
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);
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/*
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* This module implements the interconnect for pack or unpack core.
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* The interconnect is made up of NUM_STAGES stages. Each stage is made up of
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* multiple MUXs (one for each port) and a perfect shuffle.
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*
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* The number of inputs per MUX is 2**MUX_ORDER.
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* The number of ports is 2**PORT_ADDRESS_WIDTH.
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*/
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localparam NUM_PORTS = 2**PORT_ADDRESS_WIDTH;
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localparam TOTAL_DATA_WIDTH = PORT_DATA_WIDTH * NUM_PORTS;
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wire [TOTAL_DATA_WIDTH-1:0] interconnect[0:NUM_STAGES];
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assign interconnect[0] = data_in;
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assign data_out = interconnect[NUM_STAGES];
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generate
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genvar i, j;
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localparam z = 2**MUX_ORDER;
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localparam w = PORT_DATA_WIDTH;
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localparam NUM_SWITCHES = NUM_PORTS / z;
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/* Do perfect shuffle, either in forward or reverse direction */
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for (i = 0; i < NUM_STAGES; i = i + 1) begin: gen_stages
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/* Pack network are in the opposite direction */
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localparam ctrl_stage = PACK ? NUM_STAGES - i - 1 : i;
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wire [TOTAL_DATA_WIDTH-1:0] shuffle_in;
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wire [TOTAL_DATA_WIDTH-1:0] shuffle_out;
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wire [TOTAL_DATA_WIDTH-1:0] mux_in;
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wire [TOTAL_DATA_WIDTH-1:0] mux_out;
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/* Unpack uses forward shuffle and pack a reverse shuffle */
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ad_perfect_shuffle #(
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.NUM_GROUPS (PACK ? NUM_SWITCHES : z),
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.WORDS_PER_GROUP (PACK ? z : NUM_SWITCHES),
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.WORD_WIDTH (w)
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) i_shuffle (
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.data_in (shuffle_in),
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.data_out (shuffle_out)
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);
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for (j = 0; j < NUM_PORTS; j = j + 1) begin: gen_ports
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localparam ctrl_base = (ctrl_stage * NUM_PORTS + j) * MUX_ORDER;
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localparam sel_base = j & ~(z-1); /* base increments in 2**MUX_ORDER steps */
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/*
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* To be able to better share MUX control signals and reduce overall
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* resource consumption the control signal gets rotated by the offset of
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* MUX in a switch.
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*
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* E.g. a control signal of 0 for the first MUX means that the first
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* input should be selected. A control signal of 0 for the second switch
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* means that the second input will be used. To implement this (j % z)
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* is added to the control signal when selecting the input bits. This
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* addition does not result in additional resources being used. It just
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* results in a different look-up table.
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*/
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wire [MUX_ORDER-1:0] sel = ctrl[ctrl_base+:MUX_ORDER];// + j % z;
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assign mux_out[j*w+:w] = mux_in[(sel_base+sel)*w+:w];
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end
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/*
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* Pack is MUX followed by shuffle.
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* Unpack is shuffle followed by MUX.
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*/
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if (PACK) begin
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assign mux_in = interconnect[i];
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assign shuffle_in = mux_out;
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assign interconnect[i+1] = shuffle_out;
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end else begin
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assign shuffle_in = interconnect[i];
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assign mux_in = shuffle_out;
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assign interconnect[i+1] = mux_out;
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end
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end
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endgenerate
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endmodule
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