Archived
859 lines
41 KiB
Verilog
859 lines
41 KiB
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
// _ _ ____
|
|
// | | ___ ___| |__ / ___| __ _ ___
|
|
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
|
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
|
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
|
//
|
|
// Create Date: 2021/12/14 15:54:11
|
|
// Design Name:
|
|
// Module Name: system_top
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool Versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
module system_top
|
|
(
|
|
/***************************************************************************
|
|
* Contents
|
|
* 01. Clocks
|
|
* 02. AD9516 Interface
|
|
* 03. AD9361-1 Interface
|
|
* 04. AD9361-2 Interface
|
|
* 05. Phased-Array Control
|
|
* 06. RF Synthesizer Control
|
|
* 07. LVDS for Time Synchronization
|
|
* 08. Debug IO
|
|
**************************************************************************/
|
|
|
|
// *************************************************************************
|
|
// ******************************** Clocks *********************************
|
|
// *************************************************************************
|
|
// power-up configure clock
|
|
input clk_25m ,
|
|
// 250mhz backup clock
|
|
input clk_250m_p , // generated by ad9516, 250mhz
|
|
input clk_250m_n ,
|
|
// ad9361 buffered clock
|
|
input ad9361_1_buffer_clk , // derived from ad9361 input clock
|
|
input ad9361_2_buffer_clk , // derived from ad9361 input clock
|
|
// *************************************************************************
|
|
// *************************** AD9516 Interface ****************************
|
|
// *************************************************************************
|
|
// spi interface
|
|
output ad9516_spi_clk ,
|
|
output ad9516_spi_csn ,
|
|
inout ad9516_spi_mosi ,
|
|
input ad9516_spi_miso ,
|
|
// control signals
|
|
input ad9516_refmon , // ad9516 reference clock monitor
|
|
input ad9516_ld , // ad9516 lock detect
|
|
input ad9516_status , // ad9516 multiple selectable status output
|
|
output ad9516_pd_b , // ad9516 active-low power down control
|
|
output ad9516_reset_b , // ad9516 active-low reset control
|
|
output ad9516_sync_b , // ad9516 active-low manual synchronization control
|
|
// *************************************************************************
|
|
// ************************** AD9361-1 Interface ***************************
|
|
// *************************************************************************
|
|
// rx data (rx channels are tied to ground physically)
|
|
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
|
input ad9361_1_rx_frame ,
|
|
input [11:0] ad9361_1_rx_data ,
|
|
// tx data
|
|
output ad9361_1_tx_fb_clk ,
|
|
output ad9361_1_tx_frame ,
|
|
output [11:0] ad9361_1_tx_data ,
|
|
// spi interface
|
|
output ad9361_1_spi_clk ,
|
|
output ad9361_1_spi_csn ,
|
|
inout ad9361_1_spi_mosi ,
|
|
input ad9361_1_spi_miso ,
|
|
// control signals
|
|
output ad9361_1_reset_b , // ad9361 active-low reset control
|
|
output ad9361_1_en_agc , // ad9361 manual agc control
|
|
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
|
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
|
output [ 3:0] ad9361_1_ctrl_in ,
|
|
input [ 7:0] ad9361_1_ctrl_out ,
|
|
output ad9361_sync ,
|
|
// *************************************************************************
|
|
// ************************** AD9361-2 Interface ***************************
|
|
// *************************************************************************
|
|
// rx data (rx channels are tied to ground physically)
|
|
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
|
input ad9361_2_rx_frame ,
|
|
input [11:0] ad9361_2_rx_data ,
|
|
// tx data
|
|
output ad9361_2_tx_fb_clk ,
|
|
output ad9361_2_tx_frame ,
|
|
output [11:0] ad9361_2_tx_data ,
|
|
// spi interface
|
|
output ad9361_2_spi_clk ,
|
|
output ad9361_2_spi_csn ,
|
|
inout ad9361_2_spi_mosi ,
|
|
input ad9361_2_spi_miso ,
|
|
// control signals
|
|
output ad9361_2_reset_b , // ad9361 active-low reset control
|
|
output ad9361_2_en_agc , // ad9361 manual agc control
|
|
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
|
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
|
output [ 3:0] ad9361_2_ctrl_in ,
|
|
input [ 7:0] ad9361_2_ctrl_out ,
|
|
// *************************************************************************
|
|
// ************************* Phased-Array Control **************************
|
|
// *************************************************************************
|
|
output ant_cin ,
|
|
output ant_din0 ,
|
|
output ant_din1 ,
|
|
input ant_cout ,
|
|
input ant_dout0 ,
|
|
input ant_dout1 ,
|
|
output ant_tr ,
|
|
output ant_dary ,
|
|
// *************************************************************************
|
|
// ************************ RF Synthesizer Control *************************
|
|
// *************************************************************************
|
|
output rf_standby ,
|
|
output rf_sw_pll ,
|
|
output rf_t ,
|
|
output rf_r ,
|
|
output rf_sw_bpf ,
|
|
output rf_sclk1 ,
|
|
output rf_sdio1 ,
|
|
output rf_cs1 ,
|
|
input rf_ld1 ,
|
|
output rf_sclk2 ,
|
|
output rf_sdio2 ,
|
|
output rf_cs2 ,
|
|
input rf_ld2 ,
|
|
output rf_sclk3 ,
|
|
output rf_sdio3 ,
|
|
output rf_cs3 ,
|
|
input rf_ld3 ,
|
|
output rf_tmgc_16 ,
|
|
output rf_tmgc_8 ,
|
|
output rf_tmgc_4 ,
|
|
output rf_tmgc_2 ,
|
|
output rf_tmgc_1 ,
|
|
output rf_rmgc_16 ,
|
|
output rf_rmgc_8 ,
|
|
output rf_rmgc_4 ,
|
|
output rf_rmgc_2 ,
|
|
output rf_rmgc_1 ,
|
|
output rf_enable ,
|
|
output rf_sc ,
|
|
output rf_sd ,
|
|
output rf_endsyn ,
|
|
input rf_sdout ,
|
|
inout rf_dq_wd ,
|
|
output rf_sw_rx ,
|
|
// *************************************************************************
|
|
// ********************* LVDS for Time Synchronization *********************
|
|
// *************************************************************************
|
|
// 1st group
|
|
input lvds_in_1 ,
|
|
output lvds_out_1 ,
|
|
// 2nd group (these pins can be disconnected physically)
|
|
input lvds_in_2 ,
|
|
output lvds_out_2 ,
|
|
// *************************************************************************
|
|
// ******************************* Debug IO ********************************
|
|
// *************************************************************************
|
|
// 3.3v ports
|
|
output uart1_txd ,
|
|
input uart1_rxd ,
|
|
output uart2_txd ,
|
|
input uart2_rxd ,
|
|
output uart3_txd ,
|
|
input uart3_rxd ,
|
|
inout debug_io_1 ,
|
|
inout debug_io_2 ,
|
|
inout debug_io_3 ,
|
|
inout debug_io_4 ,
|
|
inout debug_io_5 ,
|
|
inout debug_io_6 ,
|
|
inout debug_io_7 ,
|
|
inout debug_io_8 ,
|
|
// 1.8v ports
|
|
inout debug_io_00_p ,
|
|
inout debug_io_01_p ,
|
|
inout debug_io_02_p ,
|
|
inout debug_io_03_p ,
|
|
inout debug_io_04_p ,
|
|
inout debug_io_05_p ,
|
|
inout debug_io_06_p ,
|
|
inout debug_io_07_p ,
|
|
inout debug_io_08_p
|
|
);
|
|
|
|
/*******************************************************************************
|
|
* Contents
|
|
* 01. Input/Output Buffer
|
|
* 02. System Clock Generation
|
|
* 03. Block Design Interface
|
|
* 04. Phased-Array Control
|
|
* 05. RF Synthesizer Control
|
|
* 06. LVDS for Time Synchronization
|
|
* 07. Tx Signals
|
|
* 08. Rx Signals
|
|
* 09. ILAs and VIOs
|
|
******************************************************************************/
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
/////////////////////////// System Clock Generation ////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// global reset
|
|
wire sys_rst ; // global reset signal, active high
|
|
wire ant_rst ; // phased-array & rf control reset signal, active high
|
|
|
|
// pl signal processing clock
|
|
wire sys_clk ; // 48MHz 41.6667MHz
|
|
wire sys_clk_2x ; // 96MHz 83.3333MHz
|
|
wire sys_clk_3x ; // 144MHz 125MHz
|
|
wire sys_clk_4x ; // 192MHz 166.6667MHz
|
|
wire sys_clk_ld ; // system main clock locked indicator
|
|
|
|
// ad9361-1 clocks
|
|
wire ad9361_1_clk ; // 48MHz 41.6667MHz
|
|
wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
|
|
wire ad9361_1_clk_3x ; // 144MHz 125MHz
|
|
wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
|
|
wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
|
|
|
|
// ad9361-2 clocks
|
|
wire ad9361_2_clk ; // 48MHz 41.6667MHz
|
|
wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
|
|
wire ad9361_2_clk_3x ; // 144MHz 125MHz
|
|
wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
|
|
wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
|
|
|
|
// phased-array & rf control clocks
|
|
wire clk_96m ;
|
|
wire clk_48m ;
|
|
wire clk_32m ;
|
|
wire clk_19p2m ;
|
|
|
|
clk_dist u_clk_dist
|
|
(
|
|
// input clocks
|
|
.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
|
|
.clk_250m_n (clk_250m_n ),
|
|
.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
|
.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
|
|
|
// output clocks & reset
|
|
// global reset
|
|
.sys_rst (sys_rst ), // global reset signal, active high
|
|
.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
|
|
|
|
// pl signal processing clock
|
|
.sys_clk (sys_clk ), // 48MHz 41.6667MHz
|
|
.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
|
|
.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
|
|
.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
|
|
.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
|
|
|
|
// ad9361-1 clocks
|
|
.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
|
|
.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
|
|
.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
|
|
.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
|
|
.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
|
|
|
|
// ad9361-2 clocks
|
|
.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
|
|
.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
|
|
.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
|
|
.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
|
|
.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
|
|
|
|
// phased-array & rf control clocks
|
|
.clk_96m (clk_96m ),
|
|
.clk_48m (clk_48m ),
|
|
.clk_32m (clk_32m ),
|
|
.clk_19p2m (clk_19p2m )
|
|
);
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////////// Block Design Interface ////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// gpio
|
|
wire [31:0] gpio_i;
|
|
wire [31:0] gpio_o;
|
|
wire ad9361_rx_fifo_rst;
|
|
wire ad9361_1_cal_start;
|
|
wire ad9361_1_cal_done;
|
|
wire ad9361_2_cal_start;
|
|
wire ad9361_2_cal_done;
|
|
wire ad9361_cal_result;
|
|
wire ad9361_recal;
|
|
|
|
assign ad9516_pd_b = gpio_o[ 0];
|
|
assign ad9516_reset_b = gpio_o[ 1];
|
|
assign ad9516_sync_b = gpio_o[ 2];
|
|
assign ad9361_1_txnrx = gpio_o[ 3]; // ad9361 enable state machine control
|
|
assign ad9361_1_enable = gpio_o[ 4]; // ad9361 enable state machine control
|
|
assign ad9361_1_en_agc = gpio_o[ 5]; // ad9361 agc control
|
|
assign ad9361_1_reset_b = gpio_o[ 6]; // ad9361 reset
|
|
assign ad9361_1_ctrl_in = gpio_o[10:7];
|
|
assign ad9361_2_txnrx = gpio_o[11]; // ad9361 enable state machine control
|
|
assign ad9361_2_enable = gpio_o[12]; // ad9361 enable state machine control
|
|
assign ad9361_2_en_agc = gpio_o[13]; // ad9361 agc control
|
|
assign ad9361_2_reset_b = gpio_o[14]; // ad9361 reset
|
|
assign ad9361_2_ctrl_in = gpio_o[18:15];
|
|
assign ad9361_sync = gpio_o[19];
|
|
assign ad9361_rx_fifo_rst = gpio_o[20];
|
|
assign ad9361_1_cal_start = gpio_o[21];
|
|
assign ad9361_2_cal_start = gpio_o[22];
|
|
assign ad9361_recal = gpio_o[23];
|
|
assign ad9361_tx_switch = gpio_o[24];
|
|
|
|
assign gpio_i[ 7:0] = ad9361_1_ctrl_out;
|
|
assign gpio_i[15:8] = ad9361_2_ctrl_out;
|
|
assign gpio_i[16] = ad9516_refmon;
|
|
assign gpio_i[17] = ad9516_ld;
|
|
assign gpio_i[18] = ad9516_status;
|
|
assign gpio_i[19] = ad9361_1_cal_done;
|
|
assign gpio_i[20] = ad9361_2_cal_done;
|
|
assign gpio_i[21] = ad9361_cal_result;
|
|
|
|
// spi interface
|
|
wire spi_sclk ;
|
|
wire [ 2:0] spi_cs ;
|
|
reg spi_sdi ;
|
|
wire spi_sdo ;
|
|
wire spi_sdo_t ;
|
|
wire spi_three_wire;
|
|
wire spi_active ;
|
|
|
|
// ad9516 - three-wire spi or four-wire spi
|
|
assign ad9516_spi_clk = spi_sclk;
|
|
assign ad9516_spi_csn = spi_cs[0];
|
|
assign ad9516_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
|
// ad9361-1 - three-wire spi or four-wire spi
|
|
assign ad9361_1_spi_clk = spi_sclk;
|
|
assign ad9361_1_spi_csn = spi_cs[1];
|
|
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
|
// ad9361-2 - three-wire spi or four-wire spi
|
|
assign ad9361_2_spi_clk = spi_sclk;
|
|
assign ad9361_2_spi_csn = spi_cs[2];
|
|
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
|
// select sdi signal
|
|
always @(*) begin
|
|
if (~ad9516_spi_csn)
|
|
spi_sdi = spi_three_wire ? ad9516_spi_mosi : ad9516_spi_miso;
|
|
else if (~ad9361_1_spi_csn)
|
|
spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
|
else if (~ad9361_2_spi_csn)
|
|
spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
|
else
|
|
spi_sdi = 1'bz;
|
|
end
|
|
|
|
// ps clock
|
|
wire ps_clk_25M;
|
|
|
|
system_bd_wrapper u_system_bd_wrapper
|
|
(
|
|
// ps system clock input
|
|
.clk_25MHz (clk_25m ), // input clk_25MHz
|
|
.ps_clk_25M (ps_clk_25M ), // output ps_clk_25M
|
|
|
|
// gpio, for control signals
|
|
.gpio_i (gpio_i ), // input [31:0]gpio_i
|
|
.gpio_o (gpio_o ), // output [31:0]gpio_o
|
|
|
|
// spi interface
|
|
.spi_sclk (spi_sclk ), // output spi_sclk
|
|
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
|
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
|
.spi_sdo (spi_sdo ), // output spi_sdo
|
|
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
|
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
|
.spi_active (spi_active ) // output spi_active
|
|
);
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
///////////////// Phased-Array & RF Synthesizer Control & C2C //////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// antenna & rf interface
|
|
wire rf_clk ;
|
|
wire rf_en ;
|
|
wire rf_data;
|
|
wire rf_tr ;
|
|
wire rf_dary;
|
|
wire rf_dout;
|
|
|
|
// output data
|
|
assign ant_cin = clk_96m;
|
|
// assign ant_din0 = accor_stream_data; // assigned afterwards
|
|
assign ant_din1 = rf_data;
|
|
assign ant_tr = rf_tr;
|
|
assign ant_dary = rf_dary;
|
|
|
|
// input data
|
|
wire ant_dout0_cdc, ant_dout1_cdc;
|
|
|
|
assign rf_dout = ant_dout1_cdc;
|
|
|
|
xpm_cdc_single u_cdc_ant_dout0
|
|
(
|
|
.dest_out (ant_dout0_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
|
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
|
|
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
|
.src_in (ant_dout0 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
|
);
|
|
|
|
xpm_cdc_single u_cdc_ant_dout1
|
|
(
|
|
.dest_out (ant_dout1_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
|
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
|
|
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
|
.src_in (ant_dout1 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
|
);
|
|
|
|
ant_rf_ctrl u_ant_rf_ctrl
|
|
(
|
|
.clk_48m (clk_48m ), // input clk_48m
|
|
.clk_96m (clk_96m ), // input clk_96m
|
|
.clk_32m (clk_32m ), // input clk_32m
|
|
.clk_19p2m (clk_19p2m ), // input clk_19p2m
|
|
.sys_rst (ant_rst ), // input sys_rst
|
|
|
|
.ant_clk (rf_clk ), // output ant_clk
|
|
.ant_en (rf_en ), // output ant_en
|
|
.ant_data (rf_data ), // output ant_data
|
|
.ant_tr (rf_tr ), // output ant_tr
|
|
.ant_dary (rf_dary ), // output ant_dary
|
|
.ant_dout (rf_dout ), // input ant_dout
|
|
|
|
.rf_standby (rf_standby ), // output rf_standby
|
|
.rf_sw_pll (rf_sw_pll ), // output rf_sw_pll
|
|
.rf_t (rf_t ), // output rf_t
|
|
.rf_r (rf_r ), // output rf_r
|
|
.rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf
|
|
.rf_sclk1 (rf_sclk1 ), // output rf_sclk1
|
|
.rf_sdio1 (rf_sdio1 ), // output rf_sdio1
|
|
.rf_cs1 (rf_cs1 ), // output rf_cs1
|
|
.rf_ld1 (rf_ld1 ), // input rf_ld1
|
|
.rf_sclk2 (rf_sclk2 ), // output rf_sclk2
|
|
.rf_sdio2 (rf_sdio2 ), // output rf_sdio2
|
|
.rf_cs2 (rf_cs2 ), // output rf_cs2
|
|
.rf_ld2 (rf_ld2 ), // input rf_ld2
|
|
.rf_sclk3 (rf_sclk3 ), // output rf_sclk3
|
|
.rf_sdio3 (rf_sdio3 ), // output rf_sdio3
|
|
.rf_cs3 (rf_cs3 ), // output rf_cs3
|
|
.rf_ld3 (rf_ld3 ), // input rf_ld3
|
|
.rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16
|
|
.rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8
|
|
.rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4
|
|
.rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2
|
|
.rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1
|
|
.rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16
|
|
.rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8
|
|
.rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4
|
|
.rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2
|
|
.rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1
|
|
.rf_enable (rf_enable ), // output rf_enable
|
|
.rf_sc (rf_sc ), // output rf_sc
|
|
.rf_sd (rf_sd ), // output rf_sd
|
|
.rf_endsyn (rf_endsyn ), // output rf_endsyn
|
|
.rf_sdout (rf_sdout ), // input rf_sdout
|
|
.rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd
|
|
.rf_sw_rx (rf_sw_rx ) // output rf_sw_rx
|
|
);
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////// LVDS for Time Synchronization /////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////// Tx Signals //////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// baseband signal
|
|
wire [11:0] tx_data_i;
|
|
wire [11:0] tx_data_q;
|
|
wire [11:0] tx_ch1_i;
|
|
wire [11:0] tx_ch1_q;
|
|
wire [11:0] tx_ch2_i;
|
|
wire [11:0] tx_ch2_q;
|
|
wire [ 3:0] bb_rshift ;
|
|
|
|
ad9361_tx_map_cmos_dual u_ad9361_tx_map
|
|
(
|
|
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
|
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
|
|
|
.tx_data_clk (sys_clk ), // input tx_data_clk
|
|
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
|
|
|
.tx_ch1_i (tx_data_i ), // input [11:0] tx_ch1_i
|
|
.tx_ch1_q (tx_data_q ), // input [11:0] tx_ch1_q
|
|
.tx_ch2_i (tx_data_i ), // input [11:0] tx_ch2_i
|
|
.tx_ch2_q (tx_data_q ), // input [11:0] tx_ch2_q
|
|
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
|
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
|
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
|
);
|
|
|
|
assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
|
|
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
|
|
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
|
|
|
|
tx_pre_process u_tx_pre_process
|
|
(
|
|
// clock & reset
|
|
.clk (sys_clk ),
|
|
.rst (sys_rst ),
|
|
// input data
|
|
.tx_data_ch1_i (tx_data_i ),
|
|
.tx_data_ch1_q (tx_data_q ),
|
|
.tx_data_ch2_i (tx_data_i ),
|
|
.tx_data_ch2_q (tx_data_q ),
|
|
// ad9361 calibration interface
|
|
.ad9361_tx_switch (ad9361_tx_switch ),
|
|
//
|
|
.bb_rshift (bb_rshift ),
|
|
// output data
|
|
.tx_ch1_i (tx_ch1_i ),
|
|
.tx_ch1_q (tx_ch1_q ),
|
|
.tx_ch2_i (tx_ch2_i ),
|
|
.tx_ch2_q (tx_ch2_q )
|
|
);
|
|
|
|
// <--------------------------------------------------------------------------->
|
|
// <--------------------- insert transmitter logic below ---------------------->
|
|
// <--------------------------------------------------------------------------->
|
|
wire [ 2:0] waveform_sel;
|
|
wire sweep_on ;
|
|
wire [31:0] freq_set ;
|
|
wire [ 1:0] iq_sel ;
|
|
|
|
tx_control u_tx_control
|
|
(
|
|
.clk (sys_clk ), // input clk
|
|
.rst (sys_rst ), // input rst
|
|
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
|
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
|
// debug ports
|
|
.waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel
|
|
.sweep_on (sweep_on ), // input sweep_on
|
|
.freq_set (freq_set ), // input [31:0] freq_set
|
|
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
|
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
|
);
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////// Rx Signals //////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
wire [11:0] rx_ch1_i, rx_ch1_q;
|
|
wire [11:0] rx_ch2_i, rx_ch2_q;
|
|
wire [11:0] rx_ch3_i, rx_ch3_q;
|
|
wire [11:0] rx_ch4_i, rx_ch4_q;
|
|
|
|
wire rx_data_valid;
|
|
wire [11:0] rx_data_i, rx_data_q;
|
|
|
|
wire hop_start_flag ;
|
|
wire accor_stream_valid ;
|
|
wire accor_stream_data ;
|
|
wire weight_stream_data ;
|
|
|
|
wire [11:0] rx_data;
|
|
|
|
assign weight_stream_data = ant_dout1_cdc;
|
|
assign ant_din0 = accor_stream_data;
|
|
|
|
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
|
|
(
|
|
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
|
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
|
|
|
.rx_data_clk (sys_clk ), // input rx_data_clk
|
|
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
|
|
|
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
|
|
|
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
|
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
|
.rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i
|
|
.rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q
|
|
.rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i
|
|
.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
|
|
);
|
|
|
|
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
|
|
(
|
|
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
|
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
|
|
|
.rx_data_clk (sys_clk ), // input rx_data_clk
|
|
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
|
|
|
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
|
|
|
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
|
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
|
.rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i
|
|
.rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q
|
|
.rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i
|
|
.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
|
|
);
|
|
|
|
rx_pre_process u_rx_pre_process
|
|
(
|
|
// clock & reset
|
|
.sys_clk (sys_clk ), // sync to adc data
|
|
.sys_clk_4x (sys_clk_4x ), // sync to physical layer
|
|
.sys_rst (sys_rst ), // sync to [sys_clk]
|
|
.clk_96m (clk_96m ), // sync to c2c data
|
|
.ant_rst (ant_rst ), // sync to [clk_96m]
|
|
// input data interface
|
|
.rx_ch1_i (rx_ch1_i ),
|
|
.rx_ch1_q (rx_ch1_q ),
|
|
.rx_ch2_i (rx_ch2_i ),
|
|
.rx_ch2_q (rx_ch2_q ),
|
|
.rx_ch3_i (rx_ch3_i ),
|
|
.rx_ch3_q (rx_ch3_q ),
|
|
.rx_ch4_i (rx_ch4_i ),
|
|
.rx_ch4_q (rx_ch4_q ),
|
|
// ad9361 calibration interface
|
|
.ad9361_1_cal_start (ad9361_1_cal_start ),
|
|
.ad9361_1_cal_done (ad9361_1_cal_done ),
|
|
.ad9361_2_cal_start (ad9361_2_cal_start ),
|
|
.ad9361_2_cal_done (ad9361_2_cal_done ),
|
|
.ad9361_cal_result (ad9361_cal_result ),
|
|
.ad9361_cal_valid (ad9361_cal_valid ),
|
|
.ad9361_recal (ad9361_recal ),
|
|
// nulling algotithm interface
|
|
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
|
|
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
|
|
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
|
|
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
|
|
.rx_data_valid (rx_data_valid ), // sync to [sys_clk]
|
|
.rx_data_i (rx_data_i ), // sync to [sys_clk]
|
|
.rx_data_q (rx_data_q ) // sync to [sys_clk]
|
|
);
|
|
|
|
// <--------------------------------------------------------------------------->
|
|
// <----------------------- insert receiver logic below ----------------------->
|
|
// <--------------------------------------------------------------------------->
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
vio_clk_ld_rd u_vio_clk_ld_rd
|
|
(
|
|
.clk (sys_clk ),
|
|
.probe_in0 (ad9361_1_clk_ld),
|
|
.probe_in1 (ad9361_2_clk_ld)
|
|
);
|
|
|
|
vio_rfcontrl u_vio_rfcontrl
|
|
(
|
|
.clk (clk_48m ), // input wire clk
|
|
.probe_out0 (u_ant_rf_ctrl.vio_switch ), // output wire [0 : 0] probe_out0
|
|
.probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1
|
|
.probe_out2 (u_ant_rf_ctrl.vio_frequency[15:0] ), // output wire [15 : 0] probe_out2
|
|
.probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3
|
|
.probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4
|
|
.probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5
|
|
.probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6
|
|
.probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7
|
|
.probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8
|
|
.probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9
|
|
.probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10
|
|
.probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11
|
|
.probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ) // output wire [15 : 0] probe_out12
|
|
);
|
|
|
|
vio_ant_test u_vio_ant_test
|
|
(
|
|
.clk (clk_48m ),
|
|
.probe_out0 (u_ant_rf_ctrl.vio_mode_ant ),
|
|
.probe_out1 (u_ant_rf_ctrl.vio_hop_start ),
|
|
.probe_out2 (u_ant_rf_ctrl.vio_standby ),
|
|
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
|
|
);
|
|
|
|
ila_rfcontrl u_ila_rfcontrl
|
|
(
|
|
.clk (clk_48m ), // input wire clk
|
|
.probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
|
.probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
|
.probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
|
.probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
|
.probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
|
.probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
|
.probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
|
.probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
|
.probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
|
.probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
|
.probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
|
.probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
|
.probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
|
.probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
|
.probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
|
.probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
|
.probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
|
.probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
|
.probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
|
.probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
|
.probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
|
.probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
|
.probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
|
.probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
|
.probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
|
.probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
|
.probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
|
.probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
|
.probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
|
.probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
|
.probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
|
.probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
|
.probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
|
.probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
|
.probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
|
.probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
|
.probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
|
.probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
|
.probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
|
.probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
|
.probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
|
.probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
|
.probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
|
.probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
|
.probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
|
.probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
|
.probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
|
.probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
|
.probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
|
.probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
|
);
|
|
|
|
ila_AntCtrl u_ila_AntCtrl
|
|
(
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
|
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
|
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
|
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
|
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
|
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
|
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
|
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
|
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
|
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
|
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
|
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
|
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
|
);
|
|
|
|
vio_rf_rd u_vio_rf_rd (
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0
|
|
.probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1
|
|
.probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2
|
|
.probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3
|
|
.probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4
|
|
.probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5
|
|
.probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6
|
|
.probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7
|
|
.probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8
|
|
.probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9
|
|
);
|
|
|
|
vio_ant_rd u_vio_ant_rd (
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
|
.probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
|
.probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
|
.probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
|
.probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
|
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
|
|
);
|
|
|
|
ila_tx_rx u_ila_tx_rx
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
|
|
.probe1 (tx_ch1_q ), // input wire [11:0] probe1
|
|
.probe2 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe2
|
|
.probe3 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe3
|
|
.probe4 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe4
|
|
.probe5 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe5
|
|
.probe6 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe6
|
|
.probe7 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe7
|
|
.probe8 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe8
|
|
.probe9 (u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe9
|
|
);
|
|
|
|
ila_cal u_ila_cal
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
|
|
.probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
|
|
.probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
|
|
.probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
|
|
.probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
|
|
.probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
|
|
.probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
|
|
.probe7 (rx_ch2_i ), // input wire [11:0] probe7
|
|
.probe8 (rx_ch2_q ), // input wire [11:0] probe8
|
|
.probe9 (rx_ch4_i ), // input wire [11:0] probe9
|
|
.probe10(rx_ch4_q ), // input wire [11:0] probe10
|
|
.probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11
|
|
.probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12
|
|
.probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13
|
|
.probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14
|
|
);
|
|
|
|
vio_cal u_vio_cal
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe_in0 (u_rx_pre_process.u_ad9361_phase_cal.relative_delay ), // input wire [4 : 0] probe_in0
|
|
.probe_in1 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff_raw ), // input wire [15 : 0] probe_in1
|
|
.probe_in2 (u_rx_pre_process.u_ad9361_phase_cal.phase_diff ) // input wire [15 : 0] probe_in2
|
|
);
|
|
|
|
ila_rx_pre u_ila_rx_pre
|
|
(
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
|
|
.probe1 (accor_stream_valid ), // input wire [0:0] probe1
|
|
.probe2 (accor_stream_data ), // input wire [0:0] probe2
|
|
.probe3 (weight_stream_data ) // input wire [0:0] probe3
|
|
);
|
|
|
|
vio_manual_ctrl u_vio_manual_ctrl
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe_out0 (waveform_sel[2:0] ), // output wire [2 : 0] probe_out0
|
|
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
|
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
|
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
|
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
|
|
);
|
|
|
|
endmodule
|