Archived
435 lines
8.6 KiB
Verilog
435 lines
8.6 KiB
Verilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
// Company:
|
|
// Engineer:
|
|
//
|
|
// Create Date: 19:54:29 09/06/2021
|
|
// Design Name:
|
|
// Module Name: mgc_ctrl
|
|
// Project Name:
|
|
// Target Devices:
|
|
// Tool versions:
|
|
// Description:
|
|
//
|
|
// Dependencies:
|
|
//
|
|
// Revision:
|
|
// Revision 0.01 - File Created
|
|
// Additional Comments:
|
|
//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
module mgc_ctrl(
|
|
input i_sys_clk ,
|
|
input i_rst_n ,
|
|
input i_TR_SW_F ,
|
|
input i_TP_EN_F ,
|
|
input i_CAL_F ,
|
|
input i_T_MGC_EN_F ,
|
|
input i_R_MGC_EN_F ,
|
|
|
|
input [15:0] i_fre_code ,
|
|
input [7:0] i_tx_mgc ,
|
|
input [7:0] i_rx1_mgc ,
|
|
input [7:0] i_rx2_mgc ,
|
|
input [7:0] i_rx3_mgc ,
|
|
input [7:0] i_rx4_mgc ,
|
|
input [3:0] i_ceshi_module,
|
|
output [15:0] o_current_fre_code,
|
|
output [15:0] o_cal_fre_code,
|
|
output [15:0] o_hop_fre_code,
|
|
output o_adf4371_hop1,
|
|
output o_adf4371_hop2,
|
|
|
|
output o_SW,
|
|
output o_SW2,
|
|
output o_SW3,
|
|
output o_SW_C1,
|
|
|
|
//发射通道MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
|
output o_T_MGC_1dB,
|
|
output o_T_MGC_2dB,
|
|
output o_T_MGC_4dB,
|
|
output o_T_MGC_8dB,
|
|
output o_T_MGC_16dB,
|
|
//接收通道1MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
|
output reg[7:0] o_R_MGC_1,
|
|
|
|
//接收通道2MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
|
output reg[7:0] o_R_MGC_2,
|
|
|
|
//接收通道3MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
|
output reg[7:0] o_R_MGC_3,
|
|
//接收通道4MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
|
output reg[7:0] o_R_MGC_4
|
|
|
|
);
|
|
|
|
|
|
reg TR_SW_F;
|
|
reg [2:0] TP_EN_r;
|
|
reg [2:0] T_MGC_EN_r;
|
|
reg [2:0] R_MGC_EN_r;
|
|
reg [2:0] R_CAL_F;
|
|
reg [15:0] hop_fre_code;
|
|
reg [15:0] current_fre_code;
|
|
wire [15:0] cal_fre_code;
|
|
reg [47:0] fre_code_a_b;
|
|
reg hop_en;
|
|
reg hop_en_r;
|
|
reg hop_en_rr;
|
|
reg cfg_en;
|
|
reg cfg_en_r;
|
|
reg cfg_en_rr;
|
|
reg hmc704_1_hop;
|
|
reg hmc704_2_hop;
|
|
reg [1:0] cnt_cfg;
|
|
reg [1:0] cnt_hop;
|
|
|
|
|
|
reg sw1;
|
|
reg sw2;
|
|
reg sw3;
|
|
reg SW_C1;
|
|
|
|
reg T_MGC_1dB_r ;
|
|
reg T_MGC_2dB_r ;
|
|
reg T_MGC_4dB_r ;
|
|
reg T_MGC_8dB_r ;
|
|
reg T_MGC_16dB_r;
|
|
|
|
assign o_SW = sw1;
|
|
assign o_SW2 = sw2;
|
|
assign o_SW3 = sw3;
|
|
assign o_SW_C1 = SW_C1;
|
|
|
|
assign o_current_fre_code= current_fre_code;
|
|
assign o_cal_fre_code = cal_fre_code;
|
|
assign o_hop_fre_code = hop_fre_code;
|
|
assign o_adf4371_hop1 = hmc704_1_hop;
|
|
assign o_adf4371_hop2 = hmc704_2_hop;
|
|
|
|
assign o_T_MGC_1dB = T_MGC_1dB_r ;
|
|
assign o_T_MGC_2dB = T_MGC_2dB_r ;
|
|
assign o_T_MGC_4dB = T_MGC_4dB_r ;
|
|
assign o_T_MGC_8dB = T_MGC_8dB_r ;
|
|
assign o_T_MGC_16dB = T_MGC_16dB_r ;
|
|
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
TR_SW_F <= 1'b0;
|
|
TP_EN_r <= 3'b0;
|
|
T_MGC_EN_r <= 3'b0;
|
|
R_MGC_EN_r <= 3'b0;
|
|
R_CAL_F <= 3'b0;
|
|
end
|
|
else begin
|
|
TR_SW_F <= i_TR_SW_F;
|
|
TP_EN_r <= {TP_EN_r[1:0] ,i_TP_EN_F};
|
|
T_MGC_EN_r <= {T_MGC_EN_r[1:0] ,i_T_MGC_EN_F};
|
|
R_MGC_EN_r <= {R_MGC_EN_r[1:0] ,i_R_MGC_EN_F};
|
|
R_CAL_F <= {R_CAL_F[1:0] ,i_CAL_F};
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
SW_C1 <= 1'b0;
|
|
current_fre_code <= 16'h6d6 ;
|
|
end
|
|
else begin
|
|
current_fre_code <= hop_en ? hop_fre_code : current_fre_code ;
|
|
if(TR_SW_F==1'b1)begin
|
|
if(current_fre_code<=1500)//20.375Ghz~21.875Ghz
|
|
SW_C1 <= 1'b1;
|
|
else //21.875Ghz~23.875Ghz
|
|
SW_C1 <= 1'b0;
|
|
end
|
|
else begin
|
|
SW_C1 <= SW_C1;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
assign cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ;
|
|
|
|
|
|
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
fre_code_a_b <= 48'h0000000006d6;
|
|
end
|
|
else if(cfg_en)begin
|
|
fre_code_a_b <= {fre_code_a_b[31:0],i_fre_code};
|
|
end
|
|
else begin
|
|
fre_code_a_b <= fre_code_a_b;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
hop_en <= 1'b0;
|
|
end
|
|
else if(TP_EN_r==3'b011)begin
|
|
hop_en <= 1'b1;
|
|
end
|
|
else begin
|
|
hop_en <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
hop_fre_code <= 16'h6d6;
|
|
end
|
|
else begin
|
|
hop_fre_code <= i_fre_code;
|
|
end
|
|
end
|
|
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
cfg_en <= 1'b0;
|
|
end
|
|
else if(hop_fre_code != i_fre_code)begin
|
|
cfg_en <= 1'b1;
|
|
end
|
|
else begin
|
|
cfg_en <= 1'b0;
|
|
end
|
|
end
|
|
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
hop_en_r <= 1'b0;
|
|
hop_en_rr <= 1'b0;
|
|
end
|
|
else begin
|
|
hop_en_r <= hop_en;
|
|
hop_en_rr <= hop_en_r;
|
|
end
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
cfg_en_r <= 1'b0;
|
|
cfg_en_rr <= 1'b0;
|
|
end
|
|
else begin
|
|
cfg_en_r <= cfg_en;
|
|
cfg_en_rr <= cfg_en_r;
|
|
end
|
|
end
|
|
|
|
reg [15:0] pre_hop_fre_code;
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
cnt_hop <= 2'b00;
|
|
end
|
|
else if(cnt_hop == 2'b10)begin
|
|
cnt_hop <= 2'b00;
|
|
end
|
|
else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin
|
|
cnt_hop <= cnt_hop + 1'b1;
|
|
end
|
|
else begin
|
|
cnt_hop <= cnt_hop;
|
|
end
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
cnt_cfg <= 2'b00;
|
|
end
|
|
else if(cnt_cfg == 2'b10)begin
|
|
cnt_cfg <= 2'b00;
|
|
end
|
|
else if(~cfg_en_r&cfg_en)begin
|
|
cnt_cfg <= cnt_cfg + 1'b1;
|
|
end
|
|
else begin
|
|
cnt_cfg <= cnt_cfg;
|
|
end
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)
|
|
pre_hop_fre_code<=16'h6d6;
|
|
else if(hop_en_rr)
|
|
pre_hop_fre_code<=hop_fre_code;
|
|
else
|
|
pre_hop_fre_code<=pre_hop_fre_code;
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
sw1 <= 1'b1;
|
|
sw2 <= 1'b1;
|
|
sw3 <= 1'b0;
|
|
end
|
|
else if(i_ceshi_module==4'ha)//自动校准开关到a
|
|
begin
|
|
sw1 <= 1'b0;
|
|
sw2 <= 1'b0;
|
|
sw3 <= 1'b1;
|
|
end
|
|
else if(i_ceshi_module==4'hb)//自动校准开关到b
|
|
begin
|
|
sw1 <= 1'b1;
|
|
sw2 <= 1'b1;
|
|
sw3 <= 1'b0;
|
|
end
|
|
else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin
|
|
if(cnt_hop == 2'b01)begin
|
|
sw1 <= 1'b0;
|
|
sw2 <= 1'b0;
|
|
sw3 <= 1'b1;
|
|
end
|
|
else begin
|
|
sw1 <= 1'b1;
|
|
sw2 <= 1'b1;
|
|
sw3 <= 1'b0;
|
|
end
|
|
end
|
|
else begin
|
|
sw1 <= sw1;
|
|
sw2 <= sw2;
|
|
sw3 <= sw3;
|
|
end
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
else if(i_ceshi_module==4'ha&&cfg_en_rr)begin
|
|
hmc704_1_hop <= 1'b1;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
else if(i_ceshi_module==4'hb&&cfg_en_rr)begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b1;
|
|
end
|
|
else if(cfg_en_rr)begin
|
|
if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
else if(cnt_cfg == 2'b01)begin
|
|
hmc704_1_hop <= 1'b1;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
else begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b1;
|
|
end
|
|
end
|
|
else begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
end
|
|
|
|
/* always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
sw1 <= 1'b1;
|
|
sw2 <= 1'b1;
|
|
sw3 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
else if(cfg_en_rr)begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b1;
|
|
end
|
|
else begin
|
|
hmc704_1_hop <= 1'b0;
|
|
hmc704_2_hop <= 1'b0;
|
|
end
|
|
end */
|
|
|
|
|
|
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
T_MGC_1dB_r <= 1'b0;
|
|
T_MGC_2dB_r <= 1'b0;
|
|
T_MGC_4dB_r <= 1'b0;
|
|
T_MGC_8dB_r <= 1'b0;
|
|
T_MGC_16dB_r <= 1'b0;
|
|
end
|
|
else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin
|
|
T_MGC_1dB_r <= 1'b0;
|
|
T_MGC_2dB_r <= 1'b0;
|
|
T_MGC_4dB_r <= 1'b0;
|
|
T_MGC_8dB_r <= 1'b0;
|
|
T_MGC_16dB_r <= 1'b0;
|
|
end
|
|
else if(T_MGC_EN_r==3'b011)begin
|
|
T_MGC_1dB_r <= i_tx_mgc[0];
|
|
T_MGC_2dB_r <= i_tx_mgc[1];
|
|
T_MGC_4dB_r <= i_tx_mgc[2];
|
|
T_MGC_8dB_r <= i_tx_mgc[3];
|
|
T_MGC_16dB_r <= i_tx_mgc[4];
|
|
end
|
|
else begin
|
|
T_MGC_1dB_r <= T_MGC_1dB_r ;
|
|
T_MGC_2dB_r <= T_MGC_2dB_r ;
|
|
T_MGC_4dB_r <= T_MGC_4dB_r ;
|
|
T_MGC_8dB_r <= T_MGC_8dB_r ;
|
|
T_MGC_16dB_r <= T_MGC_16dB_r ;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
o_R_MGC_1 <= 1'b0;
|
|
end
|
|
else if(R_MGC_EN_r==3'b011)begin
|
|
o_R_MGC_1 <= i_rx1_mgc;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
o_R_MGC_2 <= 1'b0;
|
|
end
|
|
else if(R_MGC_EN_r==3'b011)begin
|
|
o_R_MGC_2 <= i_rx2_mgc;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
o_R_MGC_3 <= 1'b0;
|
|
end
|
|
else if(R_MGC_EN_r==3'b011)begin
|
|
o_R_MGC_3 <= i_rx3_mgc;
|
|
end
|
|
end
|
|
|
|
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
|
if(!i_rst_n)begin
|
|
o_R_MGC_4 <= 1'b0;
|
|
end
|
|
else if(R_MGC_EN_r==3'b011)begin
|
|
o_R_MGC_4 <= i_rx4_mgc;
|
|
|
|
end
|
|
end
|
|
|
|
|
|
endmodule
|