Archived
11786 lines
482 KiB
XML
11786 lines
482 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>analog.com</spirit:vendor>
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<spirit:library>user</spirit:library>
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<spirit:name>axi_adxcvr</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>s_axi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:slave>
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<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
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</spirit:slave>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_awready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_wdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_wstrb</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_wvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_wready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_bresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_bvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_bready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_araddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_arprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_arvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_arready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_rdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_rresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_rvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_rready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>s_axi_aclk</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi:m_axi</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>s_axi_aresetn</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s_axi_aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>m_axi</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:master>
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<spirit:addressSpaceRef spirit:addressSpaceRef="m_axi"/>
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</spirit:master>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>AWREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_awready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WSTRB</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wstrb</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>WREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_wready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>BREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_bready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARADDR</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_araddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARPROT</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arprot</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ARREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_arready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RRESP</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rresp</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m_axi_rready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:vendorExtensions>
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<xilinx:busInterfaceInfo>
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<xilinx:enablement>
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<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.m_axi" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0">true</xilinx:isEnabled>
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</xilinx:enablement>
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</xilinx:busInterfaceInfo>
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</spirit:vendorExtensions>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>up_pll_rst</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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|
<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>up_pll_rst</spirit:name>
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</spirit:physicalPort>
|
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</spirit:portMap>
|
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</spirit:portMaps>
|
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</spirit:busInterface>
|
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<spirit:busInterface>
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<spirit:name>up_cm_0</spirit:name>
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<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
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<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
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|
<spirit:logicalPort>
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|
<spirit:name>enb</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>up_cm_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>addr</spirit:name>
|
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</spirit:logicalPort>
|
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<spirit:physicalPort>
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<spirit:name>up_cm_addr_0</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
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<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
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</spirit:logicalPort>
|
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<spirit:physicalPort>
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<spirit:name>up_cm_wr_0</spirit:name>
|
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</spirit:physicalPort>
|
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</spirit:portMap>
|
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>wdata</spirit:name>
|
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</spirit:logicalPort>
|
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<spirit:physicalPort>
|
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<spirit:name>up_cm_wdata_0</spirit:name>
|
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</spirit:physicalPort>
|
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</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
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</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
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<spirit:name>up_cm_rdata_0</spirit:name>
|
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</spirit:physicalPort>
|
|
</spirit:portMap>
|
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<spirit:portMap>
|
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<spirit:logicalPort>
|
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<spirit:name>ready</spirit:name>
|
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</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_0</spirit:name>
|
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</spirit:physicalPort>
|
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</spirit:portMap>
|
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</spirit:portMaps>
|
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<spirit:vendorExtensions>
|
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<xilinx:busInterfaceInfo>
|
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<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_0" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_0" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_0</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_0</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_1</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_1" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_1</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_1</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_1" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_2</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_2" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_2</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_2</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_3</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_3" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_3</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_3</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_3" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_4" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_4" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_4</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_4</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_4" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_5</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_5" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_5</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_5</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_5" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_6</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_6" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_6</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_6</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_6" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_7</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_7" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_7</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_7</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_7" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_8" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_8" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_8</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_8</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_8" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_9</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_9" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_9</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_9</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_9" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_10</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_10" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_10</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_10</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_10" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_11</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_11" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_11</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_11</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_11" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_cm_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_cm_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_cm_12" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_12" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_12</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_12</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_12" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_13</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_13" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_13</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_13</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_13" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_14</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_14" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_14</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_out_clk_sel_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_diffctrl</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_diffctrl_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_postcursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_postcursor_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_precursor</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_tx_precursor_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_enb_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_addr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wr_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_wdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rdata_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_ready_14</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_ch_14" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_es_15</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_cm_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>enb</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_enb_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>addr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_addr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wr</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wr_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_reset_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>wdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_wdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rdata</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_rdata_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_es_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:busInterfaceInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.up_es_15" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:busInterfaceInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>up_ch_15</spirit:name>
|
|
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="if_xcvr_ch_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>pll_locked</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_pll_locked_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>user_ready</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_user_ready_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rst_done</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rst_done_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>lpm_dfe_n</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_lpm_dfe_n_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rate</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_rate_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sys_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>up_ch_sys_clk_sel_15</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>out_clk_sel</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
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<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_sys_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_out_clk_sel_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_diffctrl_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_postcursor_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_precursor_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_enb_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_addr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_wr_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_wdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rdata_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_ready_0</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_pll_locked_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rst_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_user_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rst_done_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_lpm_dfe_n_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rate_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_sys_clk_sel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_out_clk_sel_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_diffctrl_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_postcursor_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_precursor_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
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|
|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_enb_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_addr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
</spirit:wireTypeDefs>
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_wr_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_wdata_1</spirit:name>
|
|
<spirit:wire>
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<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rdata_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
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</spirit:driver>
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</spirit:wire>
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<spirit:port>
|
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<spirit:name>up_ch_ready_1</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
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|
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|
<spirit:port>
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<spirit:name>up_es_ready_2</spirit:name>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
|
</spirit:wireTypeDefs>
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|
|
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|
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|
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|
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|
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<spirit:name>up_ch_pll_locked_2</spirit:name>
|
|
<spirit:wire>
|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_rst_2</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_user_ready_2</spirit:name>
|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_rst_done_2</spirit:name>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:name>up_ch_lpm_dfe_n_2</spirit:name>
|
|
<spirit:wire>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_rate_2</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
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|
|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
<spirit:left spirit:format="long">4</spirit:left>
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
<spirit:name>up_ch_addr_2</spirit:name>
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|
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|
<spirit:direction>out</spirit:direction>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:name>up_cm_wr_4</spirit:name>
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:port>
|
|
<spirit:name>up_cm_wdata_4</spirit:name>
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|
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|
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:name>up_cm_ready_4</spirit:name>
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|
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<spirit:name>up_es_enb_4</spirit:name>
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|
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|
<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_4</spirit:name>
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|
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|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
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|
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
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|
<spirit:name>up_es_wr_4</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
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|
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|
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|
|
<spirit:port>
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|
<spirit:name>up_es_reset_4</spirit:name>
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|
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_4</spirit:name>
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|
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|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_4</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
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|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:port>
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|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
</spirit:wireTypeDefs>
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|
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|
|
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|
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|
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|
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|
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|
<spirit:name>up_ch_pll_locked_4</spirit:name>
|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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<spirit:direction>out</spirit:direction>
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<spirit:left spirit:format="long">4</spirit:left>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:left spirit:format="long">4</spirit:left>
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</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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<spirit:name>up_ch_user_ready_8</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>up_ch_rst_done_8</spirit:name>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDefs>
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<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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</spirit:driver>
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<spirit:port>
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<spirit:name>up_ch_lpm_dfe_n_8</spirit:name>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
|
<spirit:port>
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<spirit:name>up_ch_rate_8</spirit:name>
|
|
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<spirit:direction>out</spirit:direction>
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|
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<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
<spirit:port>
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|
<spirit:name>up_ch_sys_clk_sel_8</spirit:name>
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|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
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<spirit:left spirit:format="long">1</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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<spirit:port>
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<spirit:name>up_ch_out_clk_sel_8</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
|
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<spirit:left spirit:format="long">2</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_diffctrl_8</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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</spirit:vector>
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_postcursor_8</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_precursor_8</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
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<spirit:name>up_ch_enb_8</spirit:name>
|
|
<spirit:wire>
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|
<spirit:direction>out</spirit:direction>
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
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|
</spirit:wireTypeDefs>
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|
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|
|
<spirit:port>
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|
<spirit:name>up_ch_addr_8</spirit:name>
|
|
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|
<spirit:direction>out</spirit:direction>
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|
<spirit:left spirit:format="long">11</spirit:left>
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|
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:name>up_ch_rst_9</spirit:name>
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<spirit:port>
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<spirit:name>up_ch_user_ready_9</spirit:name>
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|
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|
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|
|
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|
|
<spirit:name>up_ch_out_clk_sel_10</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_diffctrl_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
<spirit:wireTypeDef>
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|
|
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|
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|
|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_postcursor_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_precursor_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
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|
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|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
<spirit:wireTypeDef>
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|
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|
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|
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|
|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_enb_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_addr_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_wr_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_wdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_ch_rdata_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_ready_10</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
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|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_11</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_11</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_11</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_11</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
</spirit:wireTypeDefs>
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_11</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_11</spirit:name>
|
|
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|
|
<spirit:direction>in</spirit:direction>
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|
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|
<spirit:left spirit:format="long">15</spirit:left>
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
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|
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|
|
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|
|
<spirit:name>up_ch_user_ready_11</spirit:name>
|
|
<spirit:wire>
|
|
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
|
<spirit:name>up_ch_rst_done_11</spirit:name>
|
|
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|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
|
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|
|
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|
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|
|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_postcursor_12</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
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|
|
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|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_tx_precursor_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">4</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
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|
|
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|
|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_enb_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
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|
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|
</spirit:wireTypeDefs>
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|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_addr_12</spirit:name>
|
|
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|
|
<spirit:direction>out</spirit:direction>
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|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
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|
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|
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|
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
</spirit:wireTypeDefs>
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|
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|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_wr_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_wdata_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
</spirit:vector>
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|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_rdata_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
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|
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|
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<spirit:port>
|
|
<spirit:name>up_ch_ready_12</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_enb_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>up_es_addr_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">11</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wr_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_reset_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_wdata_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
<spirit:right spirit:format="long">0</spirit:right>
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|
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|
|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
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|
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_es_rdata_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long">15</spirit:left>
|
|
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|
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|
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|
|
<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
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|
|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
|
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|
|
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|
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|
|
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|
|
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|
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|
<spirit:port>
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|
|
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|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
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|
|
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|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
|
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|
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|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_rst_13</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
<spirit:name>up_ch_user_ready_13</spirit:name>
|
|
<spirit:wire>
|
|
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|
|
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|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:port>
|
|
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|
|
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|
|
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|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
<spirit:direction>out</spirit:direction>
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<spirit:left spirit:format="long">15</spirit:left>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
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|
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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|
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|
<spirit:typeName>std_logic</spirit:typeName>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:fileType>verilogSource</spirit:fileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>../../common/up_axi.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:file>
|
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<spirit:name>../../scripts/adi_xilinx_device_info_enc.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:name>axi_adxcvr.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/axi_adxcvr_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_68b2c083</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:fileSet>
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<spirit:name>xilinx_blockdiagram_view_fileset</spirit:name>
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<spirit:name>bd/bd.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:description>axi_adxcvr_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ID</spirit:name>
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<spirit:displayName>Id</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>NUM_OF_LANES</spirit:name>
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<spirit:displayName>Num Of Lanes</spirit:displayName>
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|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_LANES">8</spirit:value>
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|
</spirit:parameter>
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<spirit:parameter>
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|
<spirit:name>XCVR_TYPE</spirit:name>
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|
<spirit:displayName>Xcvr Type</spirit:displayName>
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|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.XCVR_TYPE" spirit:choiceRef="choice_pairs_07421b06">0</spirit:value>
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|
</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FPGA_TECHNOLOGY</spirit:name>
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|
<spirit:displayName>Fpga Technology</spirit:displayName>
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|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_TECHNOLOGY" spirit:choiceRef="choice_pairs_aee923ef">0</spirit:value>
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|
</spirit:parameter>
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<spirit:parameter>
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<spirit:name>FPGA_FAMILY</spirit:name>
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|
<spirit:displayName>Fpga Family</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_38e7dd38">0</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
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|
<spirit:name>SPEED_GRADE</spirit:name>
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|
<spirit:displayName>Speed Grade</spirit:displayName>
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|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SPEED_GRADE" spirit:choiceRef="choice_pairs_a535243b">0</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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|
<spirit:name>DEV_PACKAGE</spirit:name>
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|
<spirit:displayName>Dev Package</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_68effc1b">0</spirit:value>
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|
</spirit:parameter>
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<spirit:parameter>
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|
<spirit:name>FPGA_VOLTAGE</spirit:name>
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|
<spirit:displayName>Fpga Voltage</spirit:displayName>
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|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_VOLTAGE" spirit:minimum="0" spirit:maximum="5000" spirit:rangeType="long">0</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
|
|
<spirit:name>TX_OR_RX_N</spirit:name>
|
|
<spirit:displayName>Tx Or Rx N</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_OR_RX_N">0</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
|
|
<spirit:name>QPLL_ENABLE</spirit:name>
|
|
<spirit:displayName>Qpll Enable</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.QPLL_ENABLE">1</spirit:value>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>LPM_OR_DFE_N</spirit:name>
|
|
<spirit:displayName>Lpm Or Dfe N</spirit:displayName>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LPM_OR_DFE_N">1</spirit:value>
|
|
</spirit:parameter>
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|
<spirit:parameter>
|
|
<spirit:name>RATE</spirit:name>
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|
<spirit:displayName>Rate</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.RATE" spirit:bitStringLength="3">"000"</spirit:value>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_DIFFCTRL</spirit:name>
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|
<spirit:displayName>Tx Diffctrl</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_DIFFCTRL" spirit:bitStringLength="5">"01000"</spirit:value>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>TX_POSTCURSOR</spirit:name>
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|
<spirit:displayName>Tx Postcursor</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_POSTCURSOR" spirit:bitStringLength="5">"00000"</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
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|
<spirit:name>TX_PRECURSOR</spirit:name>
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|
<spirit:displayName>Tx Precursor</spirit:displayName>
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|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.TX_PRECURSOR" spirit:bitStringLength="5">"00000"</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
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|
<spirit:name>SYS_CLK_SEL</spirit:name>
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|
<spirit:displayName>Sys Clk Sel</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SYS_CLK_SEL" spirit:bitStringLength="2">"11"</spirit:value>
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|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OUT_CLK_SEL</spirit:name>
|
|
<spirit:displayName>Out Clk Sel</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.OUT_CLK_SEL" spirit:bitStringLength="3">"100"</spirit:value>
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|
</spirit:parameter>
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|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_adxcvr_v1_0</spirit:value>
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|
</spirit:parameter>
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|
</spirit:parameters>
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<spirit:vendorExtensions>
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|
<xilinx:coreExtensions>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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|
<xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>axi_adxcvr_v1_0</xilinx:displayName>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
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<xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
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<xilinx:coreRevision>1</xilinx:coreRevision>
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|
<xilinx:coreCreationDateTime>2021-12-08T12:25:35Z</xilinx:coreCreationDateTime>
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|
</xilinx:coreExtensions>
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|
<xilinx:packagingInfo>
|
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<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
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|
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="1387f2f3"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ec499260"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a638f741"/>
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