Archived
540 lines
17 KiB
Verilog
540 lines
17 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/03/23 20:17:56
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// Last Modified Date: 2023/03/10 15:41
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// Design Name:
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// Module Name: tx_qpsk
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
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// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
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// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
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// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
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// 算得出。
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_qpsk
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#(
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parameter DATA_WIDTH = 12, // need to be <= 16
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parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
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parameter BIT_DATA_LEN = 128,
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parameter SQUARE_INTERP = 8,
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parameter CLK_FREQ = 245760000 // in Hertz
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)
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(
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input clk ,
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input rst ,
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output [DATA_WIDTH-1:0] tx_data_i ,
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output [DATA_WIDTH-1:0] tx_data_q ,
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// debug ports
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input [ 1:0] waveform_sel ,
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input sweep_on ,
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input [31:0] freq_set ,
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input [ 1:0] iq_sel ,
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input [ 3:0] bb_rshift
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);
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localparam RCOS_INTERP = 64;
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localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
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localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
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////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////// Data Counter /////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// symbol & interpolation counter
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reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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cnt <= 'b0;
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end
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else begin
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cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// address
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reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
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reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
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always @(posedge clk) begin
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if (rst) begin
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hrc_data_addr_i <= 'b0;
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hrc_data_addr_q <= 'b1;
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end
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else begin
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hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
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hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
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end
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end
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// bit data
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reg hrc_data_i = 'b0;
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reg hrc_data_q = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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hrc_data_i <= 'b0;
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hrc_data_q <= 'b0;
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end
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else begin
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hrc_data_i <= BIT_DATA[hrc_data_addr_i];
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hrc_data_q <= BIT_DATA[hrc_data_addr_q];
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end
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end
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// polarization
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wire [ 7:0] hrc_data_polar_i;
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wire [ 7:0] hrc_data_polar_q;
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assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
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assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
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// root raised cosine shaping-filter
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wire [23:0] hrc_wave_i;
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wire [23:0] hrc_wave_q;
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hrc_64_12_025 u_hrc_i (
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.aclk (clk ), // input wire aclk
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.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
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.s_axis_data_tready ( ), // output wire s_axis_data_tready
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.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
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.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
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);
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hrc_64_12_025 u_hrc_q (
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.aclk (clk ), // input wire aclk
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.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
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.s_axis_data_tready ( ), // output wire s_axis_data_tready
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.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
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.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
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.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// Square Shaping Filter /////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// address
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reg [$clog2(BIT_DATA_LEN)-2 : 0] hsq_data_addr = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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hsq_data_addr <= 'b0;
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end
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else
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hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: ($clog2(BIT_DATA_LEN)-2)]};
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end
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// bit data
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reg hsq_data = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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hsq_data <= 'b0;
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end
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else begin
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hsq_data <= BIT_DATA[hsq_data_addr];
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end
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end
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// square shaping-filter
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reg [17:0] hsq_wave_i ='b0;
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reg [17:0] hsq_wave_q ='b0;
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always @(posedge clk) begin
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if (rst) begin
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hsq_wave_i <= 'b0;
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hsq_wave_q <= 'b0;
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end
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else begin
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hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
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hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////// Two Tone Siganl ////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// cosine wave with freq of 1 MHz
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wire signed [7:0] cos_1m;
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wire signed [7:0] sin_1m;
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dds_32b_8b u_dds_1m
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(
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.aclk (clk ), // input wire aclk
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.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
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.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
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.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
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.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
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);
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// two-tone signal
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reg signed [16:0] two_tone_wave_i = 'b0;
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reg signed [16:0] two_tone_wave_q = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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two_tone_wave_i <= 'b0;
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two_tone_wave_q <= 'b0;
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end
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else begin
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two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
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two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
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end
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end
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////////////////////////////////////////////////////////////////////////////////
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///////////////////// Waveform Selection & Hopping Control /////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// baseband signal select
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reg [17:0] baseband_sel_i = 'b0;
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reg [17:0] baseband_sel_q = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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baseband_sel_i <= 'b0;
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baseband_sel_q <= 'b0;
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end
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else begin
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case (waveform_sel[1:0])
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2'd0: begin
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baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
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baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
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end
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2'd1: begin
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baseband_sel_i <= hsq_wave_i[17:0];
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baseband_sel_q <= hsq_wave_q[17:0];
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end
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2'd2: begin
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baseband_sel_i <= 18'b01_1111_1111_1111_1111;
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baseband_sel_q <= 18'b0;
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end
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2'd3: begin
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baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
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baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
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end
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default: begin
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baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
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baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
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end
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endcase
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end
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end
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// hopping control, 3750hop/s
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reg [23:0] sweep_rom_addr = 'b0;
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wire [31:0] freq_sweep;
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always @(posedge clk) begin
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if (rst) begin
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sweep_rom_addr <= 'b0;
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end
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else if (sweep_on) begin
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sweep_rom_addr <= sweep_rom_addr + 24'b1;
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end
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else begin
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sweep_rom_addr <= 'b0;
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end
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end
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hop_rom u_sweep_rom
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(
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.clka (clk ), // input wire clka
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.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
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.douta (freq_sweep ) // output wire [31 : 0] douta
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);
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// choose the actual frequency word
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reg [31:0] freq_word = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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freq_word <= 'b0;
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end
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else if (sweep_on) begin
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// frequency sweep
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freq_word <= freq_sweep;
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end
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else begin
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// normal operation
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freq_word <= freq_set;
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end
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end
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// baseband frequency shift carrier generation
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wire [ 7:0] cos_dds;
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wire [ 7:0] sin_dds;
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reg [ 7:0] cos = 'b0;
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reg [ 7:0] sin = 'b0;
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dds_32b_8b u_dds_bb_shift (
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.aclk (clk ), // input wire aclk
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.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
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.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
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.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
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.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
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);
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always @(posedge clk) begin
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if (rst) begin
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cos <= 'b0;
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sin <= 'b0;
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end
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else if (freq_word == 'b0) begin
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// to make sure the carriers stay at the right position when freq = 0
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cos <= 8'b0111_1111;
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sin <= 8'b0111_1111;
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end
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else begin
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cos <= cos_dds;
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sin <= sin_dds;
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end
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end
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// baseband frequency shift modulation
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wire [47:0] mod_cmpy_a;
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wire [15:0] mod_cmpy_b;
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wire [63:0] mod_cmpy_out;
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wire [26:0] baseband_mult_i;
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wire [26:0] baseband_mult_q;
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assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
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assign mod_cmpy_b = {-sin,cos};
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assign baseband_mult_i = mod_cmpy_out[58:32];
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assign baseband_mult_q = mod_cmpy_out[26: 0];
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cmpy_18x8 u_cmpy_18x8
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(
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.aclk (clk ), // input wire aclk
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.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
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.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
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.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
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);
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// truncate to 16-bit
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reg signed [15:0] baseband_i = 'b0;
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reg signed [15:0] baseband_q = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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baseband_i <= 'b0;
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baseband_q <= 'b0;
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end
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else begin
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case (waveform_sel[1:0])
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2'd0: begin
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// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
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baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
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baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
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end
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2'd1: begin
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baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
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baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
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end
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2'd2: begin
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baseband_i <= baseband_mult_i[24:9];
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baseband_q <= baseband_mult_q[24:9];
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end
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2'd3: begin
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baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
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baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
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end
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default: begin
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// scale rasied-cosine-shaped bpsk signal by 1.125
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baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
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baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
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end
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endcase
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end
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end
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// iq selection & baseband right shift
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reg signed [15:0] baseband_data_i = 'b0;
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reg signed [15:0] baseband_data_q = 'b0;
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always @(posedge clk) begin
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if (rst) begin
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baseband_data_i <= 'b0;
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baseband_data_q <= 'b0;
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end
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else begin
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// inphase selection
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if (iq_sel[1]) begin
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baseband_data_i <= baseband_i >>> bb_rshift;
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end
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else begin
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baseband_data_i <= 'b0;
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end
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// quadrature selection
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if (iq_sel[0]) begin
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baseband_data_q <= baseband_q >>> bb_rshift;
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end
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else begin
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baseband_data_q <= 'b0;
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end
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end
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end
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// output data to ports
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assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
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assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
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endmodule
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/12/08 12:43:46
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// Design Name:
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// Module Name: tb_tx_qpsk
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// module tb_tx_qpsk;
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// reg clk = 1'b0 ;
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// reg rst = 1'b1 ;
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// reg tx_on = 1'b1 ;
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// reg [31:0] freq_set ;
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// reg [ 1:0] waveform_sel = 2'b00;
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// reg [ 1:0] iq_sel = 2'b11 ;
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// wire [11:0] tx_data_i ;
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// wire [11:0] tx_data_q ;
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// reg [ 3:0] bb_rshift = 5'b0 ;
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// tx_qpsk u_tx_qpsk
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// (
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// .clk (clk ),
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// .rst (rst ),
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// .tx_data_i (tx_data_i ),
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// .tx_data_q (tx_data_q ),
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// .waveform_sel (waveform_sel ),
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// .sweep_on (1'b0 ),
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// // .freq_set (32'd447392426 ),
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// .freq_set (32'd0 ),
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// .iq_sel (iq_sel ),
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// .bb_rshift (bb_rshift )
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// );
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// initial begin
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// #102
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// rst = 1'b0;
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// // freq_set = 32'd873813333;
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// // waveform_sel = 2'b00;
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// // bb_rshift = 5'd0;
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// // #5000
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// // bb_rshift = 5'd1;
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// // #5000
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// // bb_rshift = 5'd2;
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// // #5000
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// // bb_rshift = 5'd3;
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// // #5000
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// // bb_rshift = 5'd4;
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// // #5000
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// // bb_rshift = 5'd5;
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// // #5000
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// // bb_rshift = 5'd6;
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// // #5000
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// // bb_rshift = 5'd7;
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// // #5000
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// // bb_rshift = 5'd8;
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// // #5000
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// // bb_rshift = 5'd9;
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// // #5000
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// // bb_rshift = 5'd14;
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// // #5000
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// // bb_rshift = 5'd15;
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// // #5000
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// // bb_rshift = 5'd16;
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// // freq_set = 32'd0;
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// // func_sel = 3'b010;
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// // #7777
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// // freq_set = 32'd536870912;
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// // func_sel = 3'b100;
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// // #7777
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// // freq_set = 32'd0;
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// // func_sel = 3'b100;
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// // #7777
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// // freq_set = 32'd536870912;
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// // func_sel = 3'b010;
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// // #7777
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// // freq_set = 32'd0;
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// // func_sel = 3'b010;
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// // freq_set = 32'd536870912;
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// // iq_sel = 2'b00;
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// // #7777
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// // freq_set = 32'd536870912;
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// // iq_sel = 2'b01;
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// // #7777
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// // freq_set = 32'd536870912;
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// // iq_sel = 2'b10;
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// // #7777
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// // freq_set = 32'd536870912;
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// // iq_sel = 2'b11;
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// end
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// always #5 clk = ~clk;
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// // integer i;
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// // integer w_file;
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// // initial begin
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// // w_file = $fopen("D:\\qpsk_josh.txt","w");
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// // for (i = 0; i <= 35000; i = i + 1) begin
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// // wait(clk);
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// // #10;
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// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
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// // $signed(tx_data_q));
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// // if (i == 35000) begin
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// // $fclose(w_file);
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// // $stop;
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// // end
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// // end
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// // end
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// endmodule
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