Archived
118 lines
4.3 KiB
Verilog
118 lines
4.3 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module soft_pcs_pattern_align_tb;
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parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
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localparam [9:0] PATTERN_P = 10'b1010000011;
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localparam [9:0] PATTERN_N = 10'b0101111100;
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`define TIMEOUT 1000000
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`include "tb_base.v"
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integer counter = 0;
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reg [3:0] bitshift = 4'd0;
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reg [9:0] comma_unaligned;
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reg comma_sync = 1'b0;
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wire [9:0] comma_aligned;
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reg [9:0] comma = PATTERN_P;
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wire comma_match = comma == comma_aligned;
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always @(posedge clk) begin
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if (counter == 63) begin
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if (comma_sync != 1'b1) begin
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failed <= 1'b1;
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end
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comma_sync <= 1'b0;
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counter <= 0;
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bitshift <= {$random} % 10;
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comma <= {$random} % 2 ? PATTERN_P : PATTERN_N;
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end else begin
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counter <= counter + 1'b1;
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// Takes two clock cycles for the new value to propagate
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if (counter > 1) begin
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// Shouldn't loose sync after it gained it
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if (comma_match == 1'b1) begin
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comma_sync <= 1'b1;
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end else if (comma_sync == 1'b1) begin
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failed <= 1'b1;
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end
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end
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end
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end
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always @(*) begin
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case (bitshift)
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4'd0: comma_unaligned <= comma[9:0];
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4'd1: comma_unaligned <= {comma[0],comma[9:1]};
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4'd2: comma_unaligned <= {comma[1:0],comma[9:2]};
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4'd3: comma_unaligned <= {comma[2:0],comma[9:3]};
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4'd4: comma_unaligned <= {comma[3:0],comma[9:4]};
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4'd5: comma_unaligned <= {comma[4:0],comma[9:5]};
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4'd6: comma_unaligned <= {comma[5:0],comma[9:6]};
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4'd7: comma_unaligned <= {comma[6:0],comma[9:7]};
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4'd8: comma_unaligned <= {comma[7:0],comma[9:8]};
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default: comma_unaligned <= {comma[8:0],comma[9]};
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endcase
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end
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jesd204_pattern_align #(
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.DATA_PATH_WIDTH(1)
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) i_pa (
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.clk(clk),
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.reset(1'b0),
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.patternalign_en(1'b1),
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.in_data(comma_unaligned),
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.out_data(comma_aligned)
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);
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endmodule
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