Archived
443 lines
18 KiB
Verilog
443 lines
18 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/06/07 21:17:23
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// Design Name:
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// Module Name: system_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module system_top
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(
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// *************************************************************************
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// *************************** Clocks and Resets ***************************
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// *************************************************************************
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input sysclk_p , // FPGA_LOGIC_CLK_IN, derived from ad9528, 122.88mhz
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input sysclk_n ,
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input refclk_p , // FPGA_JESD204B_CLK_IN_1, derived from ad9528, 122.88mhz
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input refclk_n ,
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input sysref_p ,
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input sysref_n ,
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// *************************************************************************
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// *************************** AD9528 Interface ****************************
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// *************************************************************************
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// spi interface
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output spi_csn_ad9528 ,
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output spi_clk_ad9528 ,
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output spi_mosi_ad9528 ,
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input spi_miso_ad9528 ,
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// control signals
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output ad9528_reset_b ,
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output ad9528_sysref_req ,
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// *************************************************************************
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// *************************** AD9371 Interface ****************************
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// *************************************************************************
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// 204b interface, only lane 0 and lane 1 are used
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output rx_sync_p ,
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output rx_sync_n ,
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input tx_sync_p ,
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input tx_sync_n ,
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input [ 1:0] rx_data_p ,
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input [ 1:0] rx_data_n ,
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output [ 1:0] tx_data_p ,
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output [ 1:0] tx_data_n ,
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// spi interface
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output spi_csn_ad9371 ,
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output spi_clk_ad9371 ,
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output spi_mosi_ad9371 ,
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input spi_miso_ad9371 ,
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// control signals
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output ad9371_test ,
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output ad9371_reset_b ,
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input ad9371_gpint ,
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// *************************************************************************
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// ****************************** RF Control *******************************
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// *************************************************************************
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output tx_gain_5bit ,
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output tx_gain_6bit ,
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output rx_gain_3bit ,
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output rx_gain_4bit ,
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output rx_gain_5bit ,
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output tx_gain_on ,
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output rx_gain_on ,
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output [10:0] freq_hop_words ,
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output hop_words_valid ,
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output freq_hop_switch ,
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// *************************************************************************
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// ******************* DDR and Fixed-io (Do NOT Modify) ********************
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// *************************************************************************
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// ddr
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inout [14:0] ddr_addr ,
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inout [ 2:0] ddr_ba ,
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inout ddr_cas_n ,
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inout ddr_ck_n ,
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inout ddr_ck_p ,
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inout ddr_cke ,
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inout ddr_cs_n ,
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inout [ 3:0] ddr_dm ,
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inout [31:0] ddr_dq ,
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inout [ 3:0] ddr_dqs_n ,
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inout [ 3:0] ddr_dqs_p ,
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inout ddr_odt ,
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inout ddr_ras_n ,
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inout ddr_reset_n ,
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inout ddr_we_n ,
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// fixed-io
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inout fixed_io_ddr_vrn ,
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inout fixed_io_ddr_vrp ,
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inout [53:0] fixed_io_mio ,
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inout fixed_io_ps_clk ,
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inout fixed_io_ps_porb ,
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inout fixed_io_ps_srstb
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);
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////////////////////////////////////////////////////////////////////////////////
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/////////////////////////// System Clock Generation ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// system main clock, mmcm is included in block design
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wire sys_clk ; // 122.88mhz
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wire sys_rst ;
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// optional siganl clock, can be changed to whatever frequency you want
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wire sig_clk ; // 245.76mhz
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wire sig_clk_ld ;
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wire sig_rst ;
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assign sig_rst = ~sig_clk_ld;
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sig_clk_gen u_sig_clk_gen
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(
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// Clock out ports
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.clk_out1 (sig_clk ), // output clk_out1
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// Status and control signals
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.reset (sys_rst ), // input reset
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.locked (sig_clk_ld ), // output locked
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// Clock in ports
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.clk_in1 (sys_clk ) // input clk_in1
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// Block Design Interface ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// gpio
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wire [15:0] gpio_i ;
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wire [15:0] gpio_o ;
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assign gpio_i[15:5] = gpio_o[15:5];
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assign ad9528_reset_b = gpio_o[4]; // ad9528 reset pin
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assign ad9528_sysref_req = gpio_o[3]; // ad9528 sysref requset pin
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assign ad9371_test = gpio_o[2];
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assign ad9371_reset_b = gpio_o[1];
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assign gpio_i[0] = ad9371_gpint ; // ad9371 gpio interrupt pin
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// ad9371 jesd204b signals
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wire rx_rstn ;
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wire [63:0] rx_tdata ;
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wire rx_tvalid ;
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wire tx_rstn ;
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wire [63:0] tx_tdata ;
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wire tx_tready ;
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// spi interface
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wire spi_clk ;
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wire spi_mosi ;
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reg spi_miso ;
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assign spi_clk_ad9528 = spi_clk ;
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assign spi_clk_ad9371 = spi_clk ;
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assign spi_mosi_ad9528 = spi_mosi ;
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assign spi_mosi_ad9371 = spi_mosi ;
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always @(*) begin
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if (~spi_csn_ad9528)
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spi_miso = spi_miso_ad9528;
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else if (~spi_csn_ad9371)
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spi_miso = spi_miso_ad9371;
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else
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spi_miso = 1'bz;
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end
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system_bd_wrapper u_system_bd
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(
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// ddr
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.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
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.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
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.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
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.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
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.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
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.ddr_cke (ddr_cke ), // inout ddr_cke
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.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
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.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
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.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
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.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
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.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
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.ddr_odt (ddr_odt ), // inout ddr_odt
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.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
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.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
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.ddr_we_n (ddr_we_n ), // inout ddr_we_n
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// fixed io
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
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.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
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.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
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.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
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.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
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// gpio, for control signals
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.gpio_i (gpio_i[15:0] ), // input [15:0]gpio_i
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.gpio_o (gpio_o[15:0] ), // output [15:0]gpio_o
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// spi interface
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.spi_miso (spi_miso ), // input spi_miso
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.spi_mosi (spi_mosi ), // output spi_mosi
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.spi_sclk (spi_clk ), // output spi_sclk
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.spi_ss_0 (spi_csn_ad9528 ), // output spi_ss_0
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.spi_ss_1 (spi_csn_ad9371 ), // output spi_ss_1
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.spi_ss_2 ( ), // output spi_ss_2
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// system main clock
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.sysclk_p (sysclk_p ), // input sysclk_p
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.sysclk_n (sysclk_n ), // input sysclk_n
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.sys_clk (sys_clk ), // output sys_clk
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.sys_rst (sys_rst ), // output sys_rst
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// jesd 204b interface
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.refclk_p (refclk_p ), // input refclk_p
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.refclk_n (refclk_n ), // input refclk_n
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.sysref_p (sysref_p ), // input sysref_p
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.sysref_n (sysref_n ), // input sysref_n
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.rxp_in (rx_data_p[1:0] ), // input [1:0]rxp_in
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.rxn_in (rx_data_n[1:0] ), // input [1:0]rxn_in
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.rx_sync_p (rx_sync_p ), // output rx_sync_p
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.rx_sync_n (rx_sync_n ), // output rx_sync_n
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.rx_rstn (rx_rstn ), // output rx_rstn
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.rx_tdata (rx_tdata[63:0] ), // output [63:0]rx_tdata
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.rx_tvalid (rx_tvalid ), // output rx_tvalid
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.txp_out (tx_data_p[1:0] ), // output [1:0]txp_out
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.txn_out (tx_data_n[1:0] ), // output [1:0]txn_out
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.tx_sync_p (tx_sync_p ), // input tx_sync_p
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.tx_sync_n (tx_sync_n ), // input tx_sync_n
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.tx_rstn (tx_rstn ), // output tx_rstn
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.tx_tdata (tx_tdata[63:0] ), // input [63:0]tx_tdata
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.tx_tready (tx_tready ) // output tx_tready
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// RF Control Interface //////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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wire gain_on_vio ;
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wire [1:0] rf_txrx_vio ;
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wire rf_vio_set ;
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wire [5:0] tx_gain_manual ;
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wire [5:0] rx_gain_manual ;
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wire [10:0] freq_hop_words_vio ;
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wire hop_words_valid_vio ;
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wire freq_hop_switch_vio ;
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wire freq_hop_switch_out ;
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wire [11:0] tx_gain;
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wire [11:0] rx_gain;
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assign tx_gain_5bit = tx_gain[5];
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assign tx_gain_6bit = tx_gain[6];
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assign rx_gain_5bit = rx_gain[5];
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assign rx_gain_4bit = rx_gain[4];
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assign rx_gain_3bit = rx_gain[3];
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rf_control u_rf_control(
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.clk (sys_clk ),
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.rst (sys_rst ),
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//input
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.gain_on_vio (gain_on_vio ),
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.rf_txrx_vio (rf_txrx_vio[1:0] ),
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.rf_txrx_net (2'd0 ),
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.tx_gain_manual (tx_gain_manual[5:0] ),
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.rx_gain_manual (rx_gain_manual[5:0] ),
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//0:net->control 1:vio->control
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.rf_vio_set (rf_vio_set ),
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//vio hop control
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.freq_hop_words_vio (freq_hop_words_vio[10:0] ),
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.hop_words_valid_vio (hop_words_valid_vio ),
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.freq_hop_switch_vio (freq_hop_switch_vio ),
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//tx hop control
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.tx_freq_hop_words (11'b0 ),
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.tx_hop_words_valid (1'b0 ),
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.tx_freq_hop_switch (1'b0 ),
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//rx hop control
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.rx_freq_hop_words (11'b0 ),
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.rx_hop_words_valid (1'b0 ),
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.rx_freq_hop_switch (1'b0 ),
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//output
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.tx_gain (tx_gain[11:0] ),
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.tx_gain_on (tx_gain_on ),
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.rx_gain (rx_gain[9:0] ),
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.rx_gain_on (rx_gain_on ),
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.freq_hop_words (freq_hop_words[10:0] ),
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.hop_words_valid (hop_words_valid ),
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.freq_hop_switch (freq_hop_switch ),
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.freq_hop_switch_out (freq_hop_switch_out )
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);
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////////////////////////////////////////////////////////////////////////////////
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///////////////////////////// Tx Baseband Signals //////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// baseband signal
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wire [15:0] tx_1_i;
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wire [15:0] tx_1_q;
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wire [15:0] tx_2_i;
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wire [15:0] tx_2_q;
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assign tx_tdata =
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{
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tx_2_q[7:0], tx_2_q[15:8], tx_2_i[7:0], tx_2_i[15:8],
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tx_1_q[7:0], tx_1_q[15:8], tx_1_i[7:0], tx_1_i[15:8]
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};
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wire [15:0] tx_data_i;
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wire [15:0] tx_data_q;
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assign tx_1_i = tx_data_i;
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assign tx_1_q = tx_data_q;
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assign tx_2_i = tx_data_i;
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assign tx_2_q = tx_data_q;
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// <--------------------------------------------------------------------------->
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// <--------------------- insert transmitter logic below ---------------------->
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// <--------------------------------------------------------------------------->
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wire [ 1:0] waveform_sel;
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wire sweep_on ;
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wire [31:0] freq_set ;
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wire [ 1:0] iq_sel ;
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wire [ 3:0] bb_rshift ;
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tx_qpsk #(
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.DATA_WIDTH (16 ),
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.CLK_FREQ (122880000 ),
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.SQUARE_INTERP (32 )
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) u_tx_qpsk
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(
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.clk (sys_clk ), // input clk
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.rst (sys_rst ), // input rst
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.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
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.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
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// debug ports
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.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
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.sweep_on (sweep_on ), // input sweep_on
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.freq_set (freq_set ), // input [31:0] freq_set
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.iq_sel (iq_sel ), // input [ 1:0] iq_sel
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.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
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);
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////////////////////////////////////////////////////////////////////////////////
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///////////////////////////// Rx Baseband Signals //////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// rx signal
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wire [15:0] rx_1_i;
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wire [15:0] rx_1_q;
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wire [15:0] rx_2_i;
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wire [15:0] rx_2_q;
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assign rx_1_i = { rx_tdata[ 7: 0] , rx_tdata[15: 8]};
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assign rx_1_q = { rx_tdata[23:16] , rx_tdata[31:24]};
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assign rx_2_i = { rx_tdata[39:32] , rx_tdata[47:40]};
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assign rx_2_q = { rx_tdata[55:48] , rx_tdata[63:56]};
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// <--------------------------------------------------------------------------->
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// <----------------------- insert receiver logic below ----------------------->
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// <--------------------------------------------------------------------------->
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////// ILAs and VIOs /////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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ila_tx_rx u_ila_tx_rx
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(
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.clk (sys_clk ), // input wire clk
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.probe0 (rx_1_i ), // input wire [15:0] probe0
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.probe1 (rx_1_q ), // input wire [15:0] probe1
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.probe2 (rx_2_i ), // input wire [15:0] probe2
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.probe3 (rx_2_q ), // input wire [15:0] probe3
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.probe4 (tx_data_i ), // input wire [15:0] probe4
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.probe5 (tx_data_q ), // input wire [15:0] probe5
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.probe6 (rx_tvalid ), // input wire [0:0] probe6
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.probe7 (tx_tready ) // input wire [0:0] probe7
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);
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ila_ctrl_signal u_ila_ctrl_signal
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(
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.clk (sys_clk ), // input wire clk
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.probe0 (u_system_bd.system_bd_i.jesd204b.jesd_reset ), // input wire [0:0] probe0
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.probe1 (u_system_bd.system_bd_i.jesd204b.rx_sync ), // input wire [0:0] probe1
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.probe2 (rx_rstn ), // input wire [0:0] probe2
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.probe3 (u_system_bd.system_bd_i.jesd204b.tx_sync ), // input wire [0:0] probe3
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.probe4 (tx_rstn ), // input wire [0:0] probe4
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.probe5 (u_system_bd.system_bd_i.jesd204b.sysref ) // input wire [0:0] probe5
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);
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vio_manual_ctrl u_vio_manual_ctrl
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(
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.clk (sys_clk ), // input wire clk
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.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
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.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
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.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
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.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
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.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
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);
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vio_rf_control u_vio_rf_control
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(
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.clk (sys_clk ), // input wire clk
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.probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0
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.probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1
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.probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2
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.probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3
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.probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4
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.probe_out5 (freq_hop_words_vio[10:0] ), // output wire [10 : 0] probe_out5
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.probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6
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.probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7
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.probe_out8 (self_check_dout ) // output wire [0 : 0] probe_out8
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);
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endmodule
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