Archived
josh
cd256a8cd6
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137 lines
4.6 KiB
Verilog
137 lines
4.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2022/08/26 14:27:08
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// Design Name:
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// Module Name: glink_smartncnt_intf
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module glink_smartncnt_intf(
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input clk ,
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input rst_n ,
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output [31:0] glink_gpio_i_0 ,
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output [31:0] glink_gpio_i_1 ,
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input [31:0] glink_gpio_o_0 ,
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input [31:0] glink_gpio_o_1 ,
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output [11:0] i_node_id ,
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output i_node_id_par ,
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output [15:0] i_smartnc_2nd_cfg ,
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output [15:0] i_smartnc_3rd_cfg ,
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output [15:0] i_smartnt_cfg ,
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output smartnc_trans_trig ,//gpio control
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output smartnc_trans_reset ,//gpio control
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input smartnc_trans_idle ,
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input smartnc_trans_err ,//gpio control
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output [15:0] smartnc_intf_tx_fifo_wdata ,
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output smartnc_intf_tx_fifo_wr_en ,
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input smartnc_intf_tx_fifo_afull ,
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input smartnc_intf_rx_fifo_empty ,//useless
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input [15:0] smartnc_intf_rx_fifo_rdata ,//useless
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output smartnc_intf_rx_fifo_rd_en ,//useless
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input smartnt_intf_cmd_proc_req ,
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output smartnt_intf_cmd_proc_ack ,
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input smartnt_intf_rx_fifo_empty ,
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input [15:0] smartnt_intf_rx_fifo_rdata ,
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output smartnt_intf_rx_fifo_rd_en ,
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output [15:0] smartnt_intf_tx_fifo_wdata ,//useless
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output smartnt_intf_tx_fifo_wr_en ,//useless
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input [15:0] glink_tx_fifo_tdata ,
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input glink_tx_fifo_tlast ,
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output glink_tx_fifo_tready ,
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input glink_tx_fifo_tvalid ,
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output [15:0] glink_rx_fifo_tdata ,
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output glink_rx_fifo_tlast ,
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input glink_rx_fifo_tready ,
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output glink_rx_fifo_tvalid
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);
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wire smartnc_trans_trig_d0;
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//control
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assign i_node_id[11:0] = glink_gpio_o_0[11:0];
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assign i_node_id_par = ~(^i_node_id);
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assign smartnc_trans_trig_d0 = glink_gpio_o_0[12];
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assign smartnc_trans_reset = glink_gpio_o_0[13];
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assign glink_gpio_i_0[14] = smartnc_trans_idle;
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assign glink_gpio_i_0[15] = smartnc_trans_err;
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assign i_smartnt_cfg = glink_gpio_o_0[31:16];
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assign i_smartnc_2nd_cfg = glink_gpio_o_1[15:0];
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assign i_smartnc_3rd_cfg = glink_gpio_o_1[31:16];
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reg smartnc_trans_trig_d1;
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reg smartnc_trans_trig_d2;
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reg smartnc_trans_trig_d3;
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always @(posedge clk) begin
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if(~rst_n) begin
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smartnc_trans_trig_d1 <= 1'd0;
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smartnc_trans_trig_d2 <= 1'd0;
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smartnc_trans_trig_d3 <= 1'd0;
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end
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else begin
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smartnc_trans_trig_d1 <= smartnc_trans_trig_d0;
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smartnc_trans_trig_d2 <= smartnc_trans_trig_d1;
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smartnc_trans_trig_d3 <= smartnc_trans_trig_d2;
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end
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end
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assign smartnc_trans_trig = smartnc_trans_trig_d3^smartnc_trans_trig_d2;
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//useless interface
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assign smartnc_intf_rx_fifo_rd_en = 1'b0;
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assign smartnt_intf_tx_fifo_wdata = 16'b0;
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assign smartnt_intf_tx_fifo_wr_en = 1'b0;
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//stream_fifo_out to nc_tx_fifo
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assign smartnc_intf_tx_fifo_wdata = glink_tx_fifo_tdata;
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assign smartnc_intf_tx_fifo_wr_en = glink_tx_fifo_tvalid;
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assign glink_tx_fifo_tready = ~smartnc_intf_tx_fifo_afull;
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// nt_rx_fifo to stream_fifo_in
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wire glink_recv_active;
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reg glink_recv_active_d0;
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reg glink_recv_active_d1;
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reg glink_recv_active_d2;
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assign glink_recv_active = smartnt_intf_cmd_proc_req & ~smartnt_intf_rx_fifo_empty & glink_rx_fifo_tready;
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always @(posedge clk) begin
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if(~rst_n) begin
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glink_recv_active_d0 <= 1'b0;
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glink_recv_active_d1 <= 1'b0;
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glink_recv_active_d2 <= 1'b0;
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end
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else begin
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glink_recv_active_d0 <= glink_recv_active ;
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glink_recv_active_d1 <= glink_recv_active_d0 ;
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glink_recv_active_d2 <= glink_recv_active_d1 ;
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end
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end
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assign smartnt_intf_cmd_proc_ack = ~glink_recv_active_d1 & glink_recv_active_d2 ;
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assign glink_rx_fifo_tlast = ~glink_recv_active_d0 & glink_recv_active_d1 ;
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assign smartnt_intf_rx_fifo_rd_en = glink_recv_active_d1 ;
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assign glink_rx_fifo_tvalid = glink_recv_active_d1 ;
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assign glink_rx_fifo_tdata = smartnt_intf_rx_fifo_rdata ;
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endmodule
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