1.6 KiB
Vivado Git Repository
Since the day I was admitted to my lab, the vivado project management has always been a pain in the ass for me and my lab fellows. And I didn't realize how vital revision control is to a software/hardware developer until the day I accidentally overwrote the initial version of one of my modules and it's gone ever since. So after couple of days learning vivado revision control tricks, this repository came out.
The target of this repository is to stores vivado-related project and verilog/vhdl files, and maybe associated MATLAB files, or even related documentations explaining how the modules work and things needed to be taken care of when interfacing with the modules.
How this repository is constructed?
This repository include all the design sources and third-party reference used in my vivado project.
| Directory Name | Description | Synthesis Required | Implementation Required | Bitstream Required |
|---|---|---|---|---|
| adi_library | ADI no-OS IP Library, build with Xilinx Vivado 2019.1. | N/A | N/A | N/A |
| common | Common Verilog/VHDL modules that can work solely without other IPs. | Yes | No | No |
| modules | Verilog/VHDL modules that work with other IPs, thus the modules are FPGA-specific and they are managed in project mode. In the future the modules may also be categorised by different Vivado versions. | Yes | No | No |
| projects | Project or board specific vivado projects, that can be run on hardware. | Yes | Yes | Yes |
| template | Project initialization template. | N/A | N/A | N/A |