josh/vivado-202304
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josh e1399346b7 update duifei_basic_v1.0 and module ad9361_mapping 
in duifei_basic_v1.0, ila of tx and rx signal is seperated into two ilas; in module ad9361_mapping, the DDR_CLK_MODE of rx mapping iddr is changed to SAME_EDGE, and the output iq of iddr is swappedto satisfy ad9361 data interface
2023-04-06 11:16:56 +08:00
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ip
update duifei_basic_v1.0 and module ad9361_mapping
2023-04-06 11:16:56 +08:00
ipstatic
archive duifei_basic, add duifei_cal_coarse
2023-04-03 14:31:29 +08:00
mem_init_files
archive duifei_basic, add duifei_cal_coarse
2023-04-03 14:31:29 +08:00
sim_scripts
update duifei_basic_v1.0 and module ad9361_mapping
2023-04-06 11:16:56 +08:00
README.txt
archive duifei_basic, add duifei_cal_coarse
2023-04-03 14:31:29 +08:00

README.txt 

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