Archived
josh
e8a34c95e0
dl814_k7_basic is the driver instance of board smq7k410t_b9361, along with basic clock, adc and dac configurations; include nulling algorithm into dl814_z7 project
537 lines
23 KiB
Verilog
537 lines
23 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2021/12/14 15:54:11
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// Design Name:
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// Module Name: system_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module system_top
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(
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/***************************************************************************
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* Contents
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* 01. Clocks
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* 02. AD9516 Interface
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* 03. AD9361-1 Interface
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* 04. AD9361-2 Interface
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* 05. Phased-Array Control
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* 06. RF Synthesizer Control
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* 07. LVDS for Time Synchronization
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* 08. Debug IO
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**************************************************************************/
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// *************************************************************************
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// ******************************** Clocks *********************************
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// *************************************************************************
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// power-up configure clock
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input clk_25m ,
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// 250mhz backup clock
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input clk_250m_p , // generated by ad9516, 250mhz
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input clk_250m_n ,
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// ad9361 buffered clock
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input ad9361_1_buffer_clk , // derived from ad9361 input clock
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input ad9361_2_buffer_clk , // derived from ad9361 input clock
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// *************************************************************************
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// *************************** AD9516 Interface ****************************
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// *************************************************************************
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// spi interface
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output ad9516_spi_clk ,
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output ad9516_spi_csn ,
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inout ad9516_spi_mosi ,
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input ad9516_spi_miso ,
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// control signals
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input ad9516_refmon , // ad9516 reference clock monitor
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input ad9516_ld , // ad9516 lock detect
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input ad9516_status , // ad9516 multiple selectable status output
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output ad9516_pd_b , // ad9516 active-low power down control
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output ad9516_reset_b , // ad9516 active-low reset control
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output ad9516_sync_b , // ad9516 active-low manual synchronization control
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// *************************************************************************
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// ************************** AD9361-1 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
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input ad9361_1_rx_frame ,
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input [11:0] ad9361_1_rx_data ,
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// tx data
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output ad9361_1_tx_fb_clk ,
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output ad9361_1_tx_frame ,
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output [11:0] ad9361_1_tx_data ,
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// spi interface
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output ad9361_1_spi_clk ,
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output ad9361_1_spi_csn ,
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inout ad9361_1_spi_mosi ,
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input ad9361_1_spi_miso ,
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// control signals
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output ad9361_1_reset_b , // ad9361 active-low reset control
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output ad9361_1_en_agc , // ad9361 manual agc control
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output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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output [ 3:0] ad9361_1_ctrl_in ,
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input [ 7:0] ad9361_1_ctrl_out ,
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output ad9361_sync ,
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// *************************************************************************
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// ************************** AD9361-2 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
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input ad9361_2_rx_frame ,
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input [11:0] ad9361_2_rx_data ,
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// tx data
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output ad9361_2_tx_fb_clk ,
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output ad9361_2_tx_frame ,
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output [11:0] ad9361_2_tx_data ,
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// spi interface
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output ad9361_2_spi_clk ,
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output ad9361_2_spi_csn ,
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inout ad9361_2_spi_mosi ,
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input ad9361_2_spi_miso ,
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// control signals
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output ad9361_2_reset_b , // ad9361 active-low reset control
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output ad9361_2_en_agc , // ad9361 manual agc control
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output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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output [ 3:0] ad9361_2_ctrl_in ,
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input [ 7:0] ad9361_2_ctrl_out ,
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// *************************************************************************
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// ************************* Phased-Array Control **************************
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// *************************************************************************
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output ant_cin ,
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output ant_din0 ,
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output ant_din1 ,
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input ant_cout ,
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input ant_dout0 ,
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input ant_dout1 ,
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output ant_tr ,
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output ant_dary ,
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// *************************************************************************
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// ************************ RF Synthesizer Control *************************
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// *************************************************************************
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output rf_standby ,
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output rf_sw_pll ,
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output rf_t ,
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output rf_r ,
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output rf_sw_bpf ,
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output rf_sclk1 ,
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output rf_sdio1 ,
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output rf_cs1 ,
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input rf_ld1 ,
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output rf_sclk2 ,
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output rf_sdio2 ,
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output rf_cs2 ,
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input rf_ld2 ,
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output rf_sclk3 ,
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output rf_sdio3 ,
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output rf_cs3 ,
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input rf_ld3 ,
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output rf_tmgc_16 ,
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output rf_tmgc_8 ,
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output rf_tmgc_4 ,
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output rf_tmgc_2 ,
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output rf_tmgc_1 ,
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output rf_rmgc_16 ,
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output rf_rmgc_8 ,
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output rf_rmgc_4 ,
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output rf_rmgc_2 ,
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output rf_rmgc_1 ,
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output rf_enable ,
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output rf_sc ,
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output rf_sd ,
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output rf_endsyn ,
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input rf_sdout ,
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inout rf_dq_wd ,
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output rf_sw_rx ,
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// *************************************************************************
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// ********************* LVDS for Time Synchronization *********************
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// *************************************************************************
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// 1st group
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input lvds_in_1 ,
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output lvds_out_1 ,
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// 2nd group (these pins can be disconnected physically)
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input lvds_in_2 ,
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output lvds_out_2 ,
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// *************************************************************************
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// ******************************* Debug IO ********************************
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// *************************************************************************
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// 3.3v ports
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output uart1_txd ,
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input uart1_rxd ,
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output uart2_txd ,
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input uart2_rxd ,
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output uart3_txd ,
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input uart3_rxd ,
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inout debug_io_1 ,
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inout debug_io_2 ,
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inout debug_io_3 ,
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inout debug_io_4 ,
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inout debug_io_5 ,
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inout debug_io_6 ,
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inout debug_io_7 ,
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inout debug_io_8 ,
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// 1.8v ports
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inout debug_io_00_p ,
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inout debug_io_01_p ,
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inout debug_io_02_p ,
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inout debug_io_03_p ,
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inout debug_io_04_p ,
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inout debug_io_05_p ,
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inout debug_io_06_p ,
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inout debug_io_07_p ,
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inout debug_io_08_p
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);
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/*******************************************************************************
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* Contents
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* 01. Input/Output Buffer
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* 02. System Clock Generation
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* 03. Block Design Interface
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* 04. Phased-Array Control
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* 05. RF Synthesizer Control
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* 06. LVDS for Time Synchronization
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* 07. Tx Signals
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* 08. Rx Signals
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* 09. ILAs and VIOs
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******************************************************************************/
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////////////////////////////////////////////////////////////////////////////////
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/////////////////////////// System Clock Generation ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// global reset
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wire sys_rst ; // global reset signal, active high
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wire ant_rst ; // phased-array & rf control reset signal, active high
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// pl signal processing clock
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wire sys_clk ; // 48MHz 41.6667MHz
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wire sys_clk_2x ; // 96MHz 83.3333MHz
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wire sys_clk_3x ; // 144MHz 125MHz
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wire sys_clk_4x ; // 192MHz 166.6667MHz
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wire sys_clk_ld ; // system main clock locked indicator
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// ad9361-1 clocks
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wire ad9361_1_clk ; // 48MHz 41.6667MHz
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wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_1_clk_3x ; // 144MHz 125MHz
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wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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wire ad9361_2_clk ; // 48MHz 41.6667MHz
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wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_2_clk_3x ; // 144MHz 125MHz
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wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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wire clk_96m ;
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wire clk_48m ;
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wire clk_32m ;
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wire clk_19p2m ;
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clk_dist u_clk_dist
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(
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// input clocks
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.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
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.clk_250m_n (clk_250m_n ),
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.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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// output clocks & reset
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// global reset
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.sys_rst (sys_rst ), // global reset signal, active high
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.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
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// pl signal processing clock
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.sys_clk (sys_clk ), // 48MHz 41.6667MHz
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.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
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.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
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.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
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.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
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// ad9361-1 clocks
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.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
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.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
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.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
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.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
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.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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.clk_96m (clk_96m ),
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.clk_48m (clk_48m ),
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.clk_32m (clk_32m ),
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.clk_19p2m (clk_19p2m )
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// Block Design Interface ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// gpio
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire ad9361_rx_fifo_rst;
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wire ad9361_1_cal_start;
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wire ad9361_1_cal_done;
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wire ad9361_2_cal_start;
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wire ad9361_2_cal_done;
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wire ad9361_cal_result;
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wire ad9361_recal;
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assign ad9516_pd_b = gpio_o[ 0];
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assign ad9516_reset_b = gpio_o[ 1];
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assign ad9516_sync_b = gpio_o[ 2];
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assign ad9361_1_txnrx = gpio_o[ 3]; // ad9361 enable state machine control
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assign ad9361_1_enable = gpio_o[ 4]; // ad9361 enable state machine control
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assign ad9361_1_en_agc = gpio_o[ 5]; // ad9361 agc control
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assign ad9361_1_reset_b = gpio_o[ 6]; // ad9361 reset
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assign ad9361_1_ctrl_in = gpio_o[10:7];
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assign ad9361_2_txnrx = gpio_o[11]; // ad9361 enable state machine control
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assign ad9361_2_enable = gpio_o[12]; // ad9361 enable state machine control
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assign ad9361_2_en_agc = gpio_o[13]; // ad9361 agc control
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assign ad9361_2_reset_b = gpio_o[14]; // ad9361 reset
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assign ad9361_2_ctrl_in = gpio_o[18:15];
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assign ad9361_sync = gpio_o[19];
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assign ad9361_rx_fifo_rst = gpio_o[20];
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assign ad9361_1_cal_start = gpio_o[21];
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assign ad9361_2_cal_start = gpio_o[22];
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assign ad9361_recal = gpio_o[23];
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assign ad9361_tx_switch = gpio_o[24];
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assign gpio_i[ 7:0] = ad9361_1_ctrl_out;
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assign gpio_i[15:8] = ad9361_2_ctrl_out;
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assign gpio_i[16] = ad9516_refmon;
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assign gpio_i[17] = ad9516_ld;
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assign gpio_i[18] = ad9516_status;
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assign gpio_i[19] = ad9361_1_cal_done;
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assign gpio_i[20] = ad9361_2_cal_done;
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assign gpio_i[21] = ad9361_cal_result;
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// spi interface
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wire spi_sclk ;
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wire [ 2:0] spi_cs ;
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reg spi_sdi ;
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wire spi_sdo ;
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wire spi_sdo_t ;
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wire spi_three_wire;
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wire spi_active ;
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// ad9516 - three-wire spi or four-wire spi
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assign ad9516_spi_clk = spi_sclk;
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assign ad9516_spi_csn = spi_cs[0];
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assign ad9516_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// ad9361-1 - three-wire spi or four-wire spi
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assign ad9361_1_spi_clk = spi_sclk;
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assign ad9361_1_spi_csn = spi_cs[1];
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assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// ad9361-2 - three-wire spi or four-wire spi
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assign ad9361_2_spi_clk = spi_sclk;
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assign ad9361_2_spi_csn = spi_cs[2];
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assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// select sdi signal
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always @(*) begin
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if (~ad9516_spi_csn)
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spi_sdi = spi_three_wire ? ad9516_spi_mosi : ad9516_spi_miso;
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else if (~ad9361_1_spi_csn)
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spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
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else if (~ad9361_2_spi_csn)
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spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
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else
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spi_sdi = 1'bz;
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end
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// ps clock
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wire ps_clk_25M;
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system_bd_wrapper u_system_bd_wrapper
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(
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// ps system clock input
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.clk_25MHz (clk_25m ), // input clk_25MHz
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.ps_clk_25M (ps_clk_25M ), // output ps_clk_25M
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// gpio, for control signals
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.gpio_i (gpio_i ), // input [31:0]gpio_i
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.gpio_o (gpio_o ), // output [31:0]gpio_o
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// spi interface
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.spi_sclk (spi_sclk ), // output spi_sclk
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.spi_cs (spi_cs ), // output [2:0]spi_cs
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.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
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.spi_sdo (spi_sdo ), // output spi_sdo
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.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
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.spi_three_wire (spi_three_wire ), // output spi_three_wire
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.spi_active (spi_active ) // output spi_active
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);
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////////////////////////////////////////////////////////////////////////////////
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///////////////// Phased-Array & RF Synthesizer Control & C2C //////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////// LVDS for Time Synchronization /////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// Tx Signals //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// baseband signal
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wire [11:0] tx_data_i;
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wire [11:0] tx_data_q;
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wire [11:0] tx_ch1_i;
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wire [11:0] tx_ch1_q;
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wire [11:0] tx_ch2_i;
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wire [11:0] tx_ch2_q;
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ad9361_tx_map_cmos_dual u_ad9361_tx_map
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(
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.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
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.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
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.tx_data_clk (sys_clk ), // input tx_data_clk
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.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
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.tx_ch1_i (tx_data_i ), // input [11:0] tx_ch1_i
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.tx_ch1_q (tx_data_q ), // input [11:0] tx_ch1_q
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.tx_ch2_i (tx_data_i ), // input [11:0] tx_ch2_i
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.tx_ch2_q (tx_data_q ), // input [11:0] tx_ch2_q
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.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
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.tx_frame (ad9361_1_tx_frame ), // output tx_frame
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.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
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);
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assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
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// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
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// assign ad9361_2_tx_data = ad9361_1_tx_data ;
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// <--------------------------------------------------------------------------->
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// <--------------------- insert transmitter logic below ---------------------->
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// <--------------------------------------------------------------------------->
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wire [ 1:0] waveform_sel;
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wire sweep_on ;
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wire [31:0] freq_set ;
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wire [ 1:0] iq_sel ;
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wire [ 3:0] bb_rshift ;
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tx_qpsk #(
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.CLK_FREQ (48000000 )
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) u_tx_qpsk
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(
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.clk (sys_clk ), // input clk
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.rst (sys_rst ), // input rst
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.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
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.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
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// debug ports
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.waveform_sel (waveform_sel ), // input [ 1:0] waveform_sel
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.sweep_on (sweep_on ), // input sweep_on
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.freq_set (freq_set ), // input [31:0] freq_set
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.iq_sel (iq_sel ), // input [ 1:0] iq_sel
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.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
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);
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// Rx Signals //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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wire [11:0] rx_ch1_i, rx_ch1_q;
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wire [11:0] rx_ch2_i, rx_ch2_q;
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wire [11:0] rx_ch3_i, rx_ch3_q;
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wire [11:0] rx_ch4_i, rx_ch4_q;
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ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
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(
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.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
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.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
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|
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.rx_data_clk (sys_clk ), // input rx_data_clk
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.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
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|
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.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
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|
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.rx_frame (ad9361_1_rx_frame ), // input rx_frame
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.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
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.rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i
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.rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q
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.rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i
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.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
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|
);
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|
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ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
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|
(
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.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
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|
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
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|
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.rx_data_clk (sys_clk ), // input rx_data_clk
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.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
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|
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.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
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|
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.rx_frame (ad9361_2_rx_frame ), // input rx_frame
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.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
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.rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i
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.rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q
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|
.rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i
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|
.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
|
|
);
|
|
|
|
// <--------------------------------------------------------------------------->
|
|
// <----------------------- insert receiver logic below ----------------------->
|
|
// <--------------------------------------------------------------------------->
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
ila_tx_rx u_ila_tx_rx
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
|
|
.probe1 (tx_ch1_q ), // input wire [11:0] probe1
|
|
.probe2 (rx_ch1_i ), // input wire [11:0] probe2
|
|
.probe3 (rx_ch1_q ), // input wire [11:0] probe3
|
|
.probe4 (rx_ch2_i ), // input wire [11:0] probe4
|
|
.probe5 (rx_ch2_q ), // input wire [11:0] probe5
|
|
.probe6 (rx_ch3_i ), // input wire [11:0] probe6
|
|
.probe7 (rx_ch3_q ), // input wire [11:0] probe7
|
|
.probe8 (rx_ch4_i ), // input wire [11:0] probe8
|
|
.probe9 (rx_ch4_q ) // input wire [11:0] probe9
|
|
);
|
|
|
|
vio_manual_ctrl u_vio_manual_ctrl
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
|
|
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
|
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
|
|
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
|
|
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
|
|
);
|
|
|
|
endmodule
|