Archived
josh
cd256a8cd6
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450 lines
10 KiB
Verilog
450 lines
10 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2022/09/01 14:39:50
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// Design Name:
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// Module Name: antenna_interface
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module antenna_interface
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#(
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parameter [15:0] FRAME_HEAD = 16'hCCCC,
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parameter [15:0] FRAME_TAIL = 16'hF0F0,
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parameter [15:0] FRAME_LENGTH = 16'h0100,//include frame_head and frame_tail
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parameter [15:0] REST_LENGTH = 16'h0014,
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parameter [15:0] FRAME_MAX_LENGTH = 16'h0200,
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parameter [15:0] REST_MAX_LENGTH = 16'h0020
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)
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(
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input clk_in ,
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input data_in ,
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input tr_in ,
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input dary_in ,
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input rst ,
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output reg ant_clk ,
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output en_out ,
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input clk_out ,
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output data_out ,
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output tr_out ,
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output dary_out ,
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//debug
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output reg [15:0] debug_freq ,
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output reg debug_freq_change ,
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output [63:0] debug_tr_count
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);
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reg fifo_data_in ;
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wire fifo_data_out ;
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reg fifo_wr_en ;
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reg fifo_rd_en ;
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wire fifo_full ;
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wire fifo_empty ;
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wire valid ;
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fifo_en_creat u_fifo_en_creat (
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.wr_clk(clk_in), // input wire wr_clk
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.wr_rst(rst), // input wire wr_rst
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.rd_clk(clk_out), // input wire rd_clk
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.rd_rst(rst), // input wire rd_rst
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.din(fifo_data_in), // input wire [0 : 0] din
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.wr_en(fifo_wr_en), // input wire wr_en
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.rd_en(fifo_rd_en), // input wire rd_en
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.dout(fifo_data_out), // output wire [0 : 0] dout
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.full(fifo_full), // output wire full
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.empty(fifo_empty), // output wire empty
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.valid(valid) // output wire valid
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);
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reg [3:0] rx_state_next;
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reg [3:0] rx_state;
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reg [3:0] tx_state_next;
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reg [3:0] tx_state;
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localparam WAIT = 4'd0;
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localparam RECV = 4'd1;
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localparam SEND = 4'd2;
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localparam REST = 4'd3;
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//1 to 8
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reg [16:0] data_in_9;
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always @ ( posedge clk_in or posedge rst) begin
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if ( rst ) begin
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data_in_9 <= 17'd0;
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end
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else begin
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data_in_9 <= {data_in_9[15:0],data_in};
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end
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end
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//cnt
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reg [15:0] rx_bitcnt;
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always @(posedge clk_in or posedge rst) begin
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if(rst) begin
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rx_bitcnt[15:0] <= 16'd0;
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end
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else if(rx_state == RECV) begin
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rx_bitcnt[15:0] <= rx_bitcnt[15:0]+16'd1;
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end
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else begin
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rx_bitcnt[15:0] <= 16'd0;
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end
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end
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reg [15:0] tx_bitcnt;
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always @(posedge clk_out or posedge rst) begin
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if(rst) begin
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tx_bitcnt[15:0] <= 16'd0;
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end
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else if(tx_state == SEND) begin
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tx_bitcnt[15:0] <= tx_bitcnt[15:0]+16'd1;
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end
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else begin
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tx_bitcnt[15:0] <= 16'd0;
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end
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end
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reg [15:0] rest_cnt;
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always @(posedge clk_out or posedge rst) begin
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if(rst) begin
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rest_cnt[15:0] <= 16'd0;
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end
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else if(tx_state == REST) begin
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rest_cnt[15:0] <= rest_cnt[15:0]+16'd1;
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end
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else begin
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rest_cnt[15:0] <= 16'd0;
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end
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end
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// state machine
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reg recv_down;
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reg recv_down_d1;
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reg recv_down_d2;
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reg recv_down_d3;
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//rx
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always @ (*) begin
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case (rx_state)
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WAIT : begin
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if ( data_in_9[15:0] == FRAME_HEAD) begin //can write
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rx_state_next <= RECV;
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end
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else begin
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rx_state_next <= WAIT;
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end
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end
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RECV : begin // write
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if(rx_bitcnt[15:0] == FRAME_LENGTH - 16'b1) begin//write end
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rx_state_next <= WAIT;
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end
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else if(rx_bitcnt[15:0] > FRAME_MAX_LENGTH)begin //overtime
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rx_state_next <= WAIT;
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end
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else begin
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rx_state_next <= RECV;
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end
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end
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default : begin
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rx_state_next <= WAIT;
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end
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endcase
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end
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always @(posedge clk_in) begin
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rx_state <= rx_state_next;
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end
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//tx
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always @ (*) begin
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case (tx_state)
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WAIT : begin
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if (recv_down_d2^recv_down_d3) begin //can write
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tx_state_next <= SEND;
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end
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else begin
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tx_state_next <= WAIT;
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end
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end
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SEND : begin // read
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if(tx_bitcnt[15:0] == FRAME_LENGTH - 16'b1) begin//read end
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tx_state_next <= REST;
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end
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else if(tx_bitcnt[15:0] > FRAME_MAX_LENGTH)begin //overtime
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tx_state_next <= WAIT;
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end
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else begin
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tx_state_next <= SEND;
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end
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end
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REST : begin // rest
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if(rest_cnt[15:0] == REST_LENGTH - 16'b1) begin//rest end
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tx_state_next <= WAIT;
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end
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else if(rest_cnt[15:0] > REST_MAX_LENGTH)begin //overtime
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tx_state_next <= WAIT;
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end
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else begin
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tx_state_next <= REST;
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end
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end
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default : begin
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tx_state_next <= WAIT;
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end
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endcase
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end
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always @(posedge clk_out) begin
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tx_state <= tx_state_next;
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end
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//recv_down flag
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always @ ( posedge clk_in or posedge rst) begin
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if ( rst ) begin
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recv_down <= 1'b0;
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end
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else if((rx_state == RECV)&&(rx_state_next == WAIT)) begin
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recv_down <= ~recv_down;
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end
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else begin
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recv_down <= recv_down;
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end
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end
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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recv_down_d1 <= 1'b0;
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recv_down_d2 <= 1'b0;
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recv_down_d3 <= 1'b0;
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end
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else begin
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recv_down_d1 <= recv_down;
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recv_down_d2 <= recv_down_d1;
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recv_down_d3 <= recv_down_d2;
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end
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end
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//fifo control
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always @ ( posedge clk_in or posedge rst) begin
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if ( rst ) begin
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fifo_data_in <= 1'b0;
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end
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else if(rx_state == RECV) begin
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fifo_data_in <= data_in_9[16];
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end
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else begin
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fifo_data_in <= 1'b0;
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end
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end
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always @ ( posedge clk_in or posedge rst) begin
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if ( rst ) begin
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fifo_wr_en <= 1'b0;
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end
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else if(rx_state == RECV ) begin
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fifo_wr_en <= 1'b1;
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end
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else begin
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fifo_wr_en <= 1'b0;
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end
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end
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reg data_out_reg;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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data_out_reg <= 1'b0;
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end
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else if(valid) begin
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data_out_reg <= fifo_data_out;
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end
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else if(tx_state == REST) begin
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data_out_reg <= 1'b0;
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end
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else begin
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data_out_reg <= 1'b0;
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end
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end
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assign data_out = data_out_reg;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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fifo_rd_en <= 1'b0;
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end
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else if(tx_state == SEND) begin
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fifo_rd_en <= 1'b1;
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end
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else begin
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fifo_rd_en <= 1'b0;
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end
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end
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//en create
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reg en_out_reg;
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reg en_out_reg_d1;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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en_out_reg <= 1'b1;
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en_out_reg_d1 <= 1'b1;
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end
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else begin
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en_out_reg <= ~fifo_rd_en;
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en_out_reg_d1 <= en_out_reg;
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end
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end
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assign en_out = en_out_reg_d1;
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//beam_clk
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wire beam_clk;
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reg beam_clk_reg;
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reg beam_clk_reg_d1;
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reg beam_clk_reg_d2;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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beam_clk_reg <= 1'b0;
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end
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else if(tx_state == SEND || tx_state == REST) begin
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beam_clk_reg <= 1'b1;
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end
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else begin
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beam_clk_reg <= 1'b0;
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end
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end
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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beam_clk_reg_d1 <= 1'b0;
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beam_clk_reg_d2 <= 1'b0;
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end
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else begin
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beam_clk_reg_d1 <= beam_clk_reg;
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beam_clk_reg_d2 <= beam_clk_reg_d1;
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end
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end
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assign beam_clk = beam_clk_reg_d2;
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//tr dary
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reg tr_d1;
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reg tr_d2;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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tr_d1 <= 1'b0;
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tr_d2 <= 1'b0;
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end
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else begin
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tr_d1 <= tr_in;
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tr_d2 <= tr_d1;
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end
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end
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assign tr_out = tr_d2;
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reg dary_d1;
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reg dary_d2;
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always @ ( posedge clk_out or posedge rst) begin
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if ( rst ) begin
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dary_d1 <= 1'b0;
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dary_d2 <= 1'b0;
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end
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else begin
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dary_d1 <= dary_in;
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dary_d2 <= dary_d1;
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end
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end
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assign dary_out = dary_d2;
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//ant_clk
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reg valid_d1;
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always @ ( posedge clk_out or posedge rst) begin
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if (rst ) begin
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valid_d1 <= 1'b0;
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end
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else begin
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valid_d1 <= valid;
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end
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end
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always @ ( posedge clk_out or posedge rst) begin
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if (rst ) begin
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ant_clk <= 1'b1;
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end
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else if(~valid_d1 && valid) begin
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ant_clk <= 1'b1;
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end
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else if(beam_clk) begin
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ant_clk <= ~ant_clk;
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end
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else begin
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ant_clk <= 1'b1;
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end
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end
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//debug
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reg [31:0] freq;
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always @ ( posedge clk_out or posedge rst) begin
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if (rst ) begin
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freq[31:0] <= 32'b0;
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end
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else begin
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freq[31:0] <= {freq[30:0],data_out_reg};
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end
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end
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always @ ( posedge clk_out or posedge rst) begin
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if (rst ) begin
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debug_freq[15:0] <= 16'b0;
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end
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else if(tx_bitcnt == 16'h0092) begin
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debug_freq[15:0] <= {freq[30],freq[28],freq[26],freq[24],freq[22],freq[20],freq[18],freq[16],freq[14],freq[12],freq[10],freq[8],freq[6],freq[4],freq[2],freq[0]};
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end
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else begin
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debug_freq[15:0] <= debug_freq[15:0];
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end
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end
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always @ ( posedge clk_out or posedge rst) begin
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if (rst ) begin
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debug_freq_change <= 1'b0;
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end
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else if(tx_bitcnt == 16'h0092 || tx_bitcnt == 16'h0093) begin
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debug_freq_change <= 1'b1;
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end
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else begin
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debug_freq_change <= 1'b0;
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end
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end
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assign debug_tr_count = 64'b0;
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// always @ ( posedge clk_out or posedge rst) begin
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// if (rst ) begin
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// debug_tr_count[63:0] <= 64'b0;
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// end
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// else if(tr_d1 != tr_d2) begin
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// debug_tr_count[63:0] <= 64'b0;
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// end
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// else begin
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// debug_tr_count[63:0] <= debug_tr_count[63:0] + 64'b1;
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// end
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// end
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endmodule
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