Archived
142 lines
4.5 KiB
Verilog
142 lines
4.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_cmos_if #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter CLK_DESKEW = 0,
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parameter USE_SSI_CLK = 1,
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// Dummy parameters, required keep the code consistency(used on Xilinx)
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter DELAY_REFCLK_FREQUENCY = 0) (
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// physical interface (receive)
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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// physical interface (transmit)
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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// ensm control
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output enable,
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output txnrx,
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// clock (common to both receive and transmit)
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input rst,
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input clk,
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output l_clk,
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// receive data path interface
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output adc_valid,
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output [47:0] adc_data,
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output adc_status,
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input adc_r1_mode,
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input adc_ddr_edgesel,
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// transmit data path interface
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input dac_valid,
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input [47:0] dac_data,
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input dac_clksel,
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input dac_r1_mode,
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// tdd interface
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input tdd_enable,
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input tdd_txnrx,
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input tdd_mode,
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// delay interface
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input mmcm_rst,
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input up_clk,
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input up_rstn,
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input up_enable,
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input up_txnrx,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input [15:0] up_dac_dld,
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input [79:0] up_dac_dwdata,
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output [79:0] up_dac_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked,
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// drp interface
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked);
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// cmos is not supported on intel platforms yet.
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assign tx_clk_out = 1'd0;
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assign tx_frame_out = 1'd0;
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assign tx_data_out = 12'd0;
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assign enable = 1'd0;
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assign txnrx = 1'd0;
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assign l_clk = 1'd0;
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assign adc_valid = 1'd0;
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assign adc_data = 48'd0;
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assign adc_status = 1'd0;
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assign up_adc_drdata = 65'd0;
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assign up_dac_drdata = 80'd0;
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assign delay_locked = 1'd0;
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assign up_drp_rdata = 32'd0;
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assign up_drp_ready = 1'd0;
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assign up_drp_locked = 1'd0;
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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