xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
