vio_clk_ld_rd.v,verilog,xil_defaultlib,../../../ip/vio_clk_ld_rd/sim/vio_clk_ld_rd.v,incdir="../../../ip/vio_clk_ld_rd/hdl/verilog"incdir="../../../ip/vio_clk_ld_rd/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
