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update dl814_dj_new_48m; fix bug in phase_comp

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单独的地检射频控制模块使用外部输入时钟驱动VIO,而非计数器产生的12M时钟;修复相位补偿输出为0的问题,时钟和复位信号接反
This commit is contained in:
josh
2023-05-24 14:36:15 +08:00
parent a476d6f42e
commit 05572f3d8e
22 changed files with 5989 additions and 403 deletions
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projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc
-1
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@@ -2,7 +2,6 @@
## Timing Assertions Section
create_clock -period 8.000 [get_ports refclk_p]
create_clock -period 80.000 [get_ports clk_12M]
## Physical Constraints Section
projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx
+10 -13
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@@ -10,7 +10,8 @@
{
"type": "XSDB_V3",
"name": "dbg_hub",
"spec": "labtools_xsdbm_v3"
"spec": "labtools_xsdbm_v3",
"clk_input_freq_hz": "122880320"
},
{
"type": "ILA_V3",
@@ -2468,26 +2469,22 @@
"parent_nets": [
{
"id": 18,
"name": "u_rf_control/clk_12M_BUFG",
"name": "u_rf_control/clk_12M",
"state_reg": [
{
"name": "ila_rf_test/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/current_state_reg[0]",
"name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]",
"states": [
{
"name": "REG",
"val": "0010"
"name": "iSTATE",
"val": "00"
},
{
"name": "P2S",
"val": "0100"
"name": "iSTATE0",
"val": "01"
},
{
"name": "IDLE",
"val": "0001"
},
{
"name": "S2P",
"val": "1000"
"name": "iSTATE1",
"val": "10"
}
]
}
projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit
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projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx
+10 -13
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@@ -10,7 +10,8 @@
{
"type": "XSDB_V3",
"name": "dbg_hub",
"spec": "labtools_xsdbm_v3"
"spec": "labtools_xsdbm_v3",
"clk_input_freq_hz": "122880320"
},
{
"type": "ILA_V3",
@@ -2468,26 +2469,22 @@
"parent_nets": [
{
"id": 18,
"name": "u_rf_control/clk_12M_BUFG",
"name": "u_rf_control/clk_12M",
"state_reg": [
{
"name": "ila_rf_test/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/current_state_reg[0]",
"name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]",
"states": [
{
"name": "REG",
"val": "0010"
"name": "iSTATE",
"val": "00"
},
{
"name": "P2S",
"val": "0100"
"name": "iSTATE0",
"val": "01"
},
{
"name": "IDLE",
"val": "0001"
},
{
"name": "S2P",
"val": "1000"
"name": "iSTATE1",
"val": "10"
}
]
}
projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf
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projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v
+1 -1
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@@ -211,7 +211,7 @@ module rf_control(
wire [7:0] MOSI_rx_atte ;
// 发送使能输入vio_rftx_en
vio_rf_test vio_rf_test (
.clk(clk_12M), // input wire clk
.clk(clk), // input wire clk
.probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0
.probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0
.probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0