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update dl814_dj_new_48m; fix bug in phase_comp

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单独的地检射频控制模块使用外部输入时钟驱动VIO,而非计数器产生的12M时钟;修复相位补偿输出为0的问题,时钟和复位信号接反
This commit is contained in:
josh
2023-05-24 14:36:15 +08:00
parent a476d6f42e
commit 05572f3d8e
22 changed files with 5989 additions and 403 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/project.tcl
+11 -11
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@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Sun May 21 17:14:02 CST 2023
# Generated by Vivado on Wed May 24 14:32:42 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -34,7 +34,7 @@
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_cal/ila_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
@@ -219,15 +219,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "90" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "90" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "90" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "91" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "91" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "91" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "90" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "90" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "90" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "91" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "91" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "91" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "90" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "91" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -252,7 +252,7 @@ set files [list \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
@@ -391,7 +391,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
set file "$origin_dir/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit
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projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf
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projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/phase_comp.v
+1 -1
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@@ -28,8 +28,8 @@ module phase_comp
)
(
// clock & reset
input rst ,
input clk ,
input rst ,
// input data
input din_valid ,
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v
+2 -2
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@@ -175,8 +175,8 @@ phase_comp #(
) u_phase_comp
(
// clock & reset
.rst (sys_clk ),
.clk (sys_rst ),
.clk (sys_clk ),
.rst (sys_rst ),
// input data
.din_valid (phase_comp_din_valid ),
projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+2 -1
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@@ -908,7 +908,7 @@ vio_rf_rd u_vio_rf_rd (
// .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
// );
ila_2x12x131072 u_ila_tx
ila_2x12x1024 u_ila_tx
(
.clk (sys_clk ), // input wire clk
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
@@ -1007,4 +1007,5 @@ vio_phase_comp u_vio_phase_comp
.probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2
.probe_out3 (phase_ch4 ) // output wire [15 : 0] probe_out3
);
endmodule