Archived
update dl814_dj_new_48m; fix bug in phase_comp
单独的地检射频控制模块使用外部输入时钟驱动VIO,而非计数器产生的12M时钟;修复相位补偿输出为0的问题,时钟和复位信号接反
This commit is contained in:
@@ -2,7 +2,6 @@
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## Timing Assertions Section
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create_clock -period 8.000 [get_ports refclk_p]
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create_clock -period 80.000 [get_ports clk_12M]
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## Physical Constraints Section
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@@ -10,7 +10,8 @@
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3"
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "122880320"
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},
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{
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"type": "ILA_V3",
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@@ -2468,26 +2469,22 @@
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"parent_nets": [
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{
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"id": 18,
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"name": "u_rf_control/clk_12M_BUFG",
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"name": "u_rf_control/clk_12M",
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"state_reg": [
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{
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"name": "ila_rf_test/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/current_state_reg[0]",
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"name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]",
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"states": [
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{
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"name": "REG",
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"val": "0010"
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"name": "iSTATE",
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"val": "00"
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},
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{
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"name": "P2S",
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"val": "0100"
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"name": "iSTATE0",
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"val": "01"
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},
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{
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"name": "IDLE",
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"val": "0001"
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},
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{
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"name": "S2P",
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"val": "1000"
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"name": "iSTATE1",
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"val": "10"
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}
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]
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}
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Binary file not shown.
@@ -10,7 +10,8 @@
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{
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"type": "XSDB_V3",
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"name": "dbg_hub",
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"spec": "labtools_xsdbm_v3"
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"spec": "labtools_xsdbm_v3",
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"clk_input_freq_hz": "122880320"
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},
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{
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"type": "ILA_V3",
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@@ -2468,26 +2469,22 @@
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"parent_nets": [
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{
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"id": 18,
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"name": "u_rf_control/clk_12M_BUFG",
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"name": "u_rf_control/clk_12M",
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"state_reg": [
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{
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"name": "ila_rf_test/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/current_state_reg[0]",
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"name": "u_rf_control/FSM_sequential_state_MOSI_reg[0]",
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"states": [
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{
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"name": "REG",
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"val": "0010"
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"name": "iSTATE",
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"val": "00"
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},
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{
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"name": "P2S",
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"val": "0100"
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"name": "iSTATE0",
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"val": "01"
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},
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{
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"name": "IDLE",
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"val": "0001"
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},
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{
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"name": "S2P",
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"val": "1000"
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"name": "iSTATE1",
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"val": "10"
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}
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]
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}
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Binary file not shown.
@@ -211,7 +211,7 @@ module rf_control(
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wire [7:0] MOSI_rx_atte ;
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// 发送使能输入vio_rftx_en
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vio_rf_test vio_rf_test (
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.clk(clk_12M), // input wire clk
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.clk(clk), // input wire clk
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.probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0
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.probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0
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.probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0
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@@ -3,7 +3,7 @@
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#
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# project.tcl: Tcl script for re-creating project 'project'
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#
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# Generated by Vivado on Sun May 21 17:14:02 CST 2023
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# Generated by Vivado on Wed May 24 14:32:42 CST 2023
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# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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@@ -34,7 +34,7 @@
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_cal/ila_cal.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
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# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
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@@ -219,15 +219,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
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set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
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set_property -name "simulator_language" -value "Mixed" -objects $obj
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set_property -name "target_simulator" -value "VCS" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.ies_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.activehdl_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.ies_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.modelsim_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
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set_property -name "webtalk.questa_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.riviera_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.vcs_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.questa_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.riviera_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.vcs_export_sim" -value "91" -objects $obj
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set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj
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set_property -name "webtalk.xsim_export_sim" -value "90" -objects $obj
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set_property -name "webtalk.xsim_export_sim" -value "91" -objects $obj
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set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
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# Create 'sources_1' fileset (if not found)
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@@ -252,7 +252,7 @@ set files [list \
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[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"] \
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[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"] \
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[file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"] \
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[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"] \
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[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \
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[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \
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[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
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[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
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@@ -391,7 +391,7 @@ if { ![get_property "is_locked" $file_obj] } {
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set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
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}
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set file "$origin_dir/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
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set file "$origin_dir/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
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Binary file not shown.
Binary file not shown.
@@ -28,8 +28,8 @@ module phase_comp
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)
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(
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// clock & reset
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input rst ,
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input clk ,
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input rst ,
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// input data
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input din_valid ,
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@@ -175,8 +175,8 @@ phase_comp #(
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) u_phase_comp
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(
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// clock & reset
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.rst (sys_clk ),
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.clk (sys_rst ),
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.clk (sys_clk ),
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.rst (sys_rst ),
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// input data
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.din_valid (phase_comp_din_valid ),
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@@ -908,7 +908,7 @@ vio_rf_rd u_vio_rf_rd (
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// .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
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// );
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ila_2x12x131072 u_ila_tx
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ila_2x12x1024 u_ila_tx
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(
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.clk (sys_clk ), // input wire clk
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.probe0 (tx_ch1_i ), // input wire [11:0] probe0
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@@ -1007,4 +1007,5 @@ vio_phase_comp u_vio_phase_comp
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.probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2
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.probe_out3 (phase_ch4 ) // output wire [15 : 0] probe_out3
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);
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endmodule
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+4
-4
@@ -1,10 +1,10 @@
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version:1
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||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3430:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3431:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:313130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7079697068616e646c65725f64657374696e6174696f6e5f69705f6e616d65:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3634:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3530:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:343436:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:36:00:00
|
||||
@@ -33,9 +33,9 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3630:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f65646974:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f697073796d626f6c5f73686f775f64697361626c65645f706f727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f74616262656470616e655f7461626265645f70616e65:3132:00:00
|
||||
eof:2158482477
|
||||
eof:705714440
|
||||
|
||||
+3
-3
@@ -2,11 +2,11 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3930:00:00
|
||||
eof:1876082269
|
||||
eof:3167550
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:28
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:29
|
||||
eof:
|
||||
|
||||
+6
-6
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun May 21 16:53:49 2023">
|
||||
<application name="pa" timeStamp="Tue May 23 08:24:22 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -20,21 +20,21 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="AddExistingIPHandler" value="15" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="17" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="10" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="19" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="20" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="22" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="4" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="4" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="24" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="25" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="90" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="40" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="41" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="110" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="6" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="10" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="61" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="64" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="50" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="446" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="6" type="GuiHandlerData"/>
|
||||
@@ -63,7 +63,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="60" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="12" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="27" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="28" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="6" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_EDIT" value="1" type="GuiHandlerData"/>
|
||||
<property name="XPG_IPSymbol_SHOW_DISABLED_PORTS" value="2" type="GuiHandlerData"/>
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
#
|
||||
# project.tcl: Tcl script for re-creating project 'project'
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 17:13:05 CST 2023
|
||||
# Generated by Vivado on Wed May 24 14:19:39 CST 2023
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
@@ -33,7 +33,10 @@
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_cal/ila_cal.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/mult_18x18/mult_18x18.xci"
|
||||
@@ -89,8 +92,6 @@
|
||||
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
|
||||
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/coe/freq_word.coe"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
|
||||
# "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
|
||||
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"
|
||||
@@ -207,15 +208,16 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "target_simulator" -value "VCS" -objects $obj
|
||||
set_property -name "webtalk.activehdl_export_sim" -value "121" -objects $obj
|
||||
set_property -name "webtalk.ies_export_sim" -value "121" -objects $obj
|
||||
set_property -name "webtalk.modelsim_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.activehdl_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.ies_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.modelsim_export_sim" -value "123" -objects $obj
|
||||
set_property -name "webtalk.modelsim_launch_sim" -value "4" -objects $obj
|
||||
set_property -name "webtalk.questa_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.riviera_export_sim" -value "121" -objects $obj
|
||||
set_property -name "webtalk.vcs_export_sim" -value "121" -objects $obj
|
||||
set_property -name "webtalk.questa_export_sim" -value "123" -objects $obj
|
||||
set_property -name "webtalk.riviera_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.vcs_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.vcs_launch_sim" -value "264" -objects $obj
|
||||
set_property -name "webtalk.xsim_export_sim" -value "122" -objects $obj
|
||||
set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj
|
||||
set_property -name "webtalk.xsim_export_sim" -value "123" -objects $obj
|
||||
set_property -name "webtalk.xsim_launch_sim" -value "2" -objects $obj
|
||||
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
|
||||
|
||||
@@ -240,7 +242,10 @@ set files [list \
|
||||
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"] \
|
||||
[file normalize "${origin_dir}/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"] \
|
||||
[file normalize "${origin_dir}/ip/vio_rfcontrl/vio_rfcontrl.xci"] \
|
||||
[file normalize "${origin_dir}/ip/mult_18x18/mult_18x18.xci"] \
|
||||
@@ -296,8 +301,6 @@ set files [list \
|
||||
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
|
||||
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
|
||||
[file normalize "${origin_dir}/ip/coe/freq_word.coe"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
|
||||
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
|
||||
[file normalize "${origin_dir}/../../../common/ApproxModuli_26bit.v"] \
|
||||
[file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \
|
||||
[file normalize "${origin_dir}/../common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \
|
||||
@@ -359,6 +362,15 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
@@ -368,6 +380,24 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
@@ -526,24 +556,6 @@ if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
set file "$origin_dir/../common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
|
||||
+2908
-118
File diff suppressed because it is too large
Load Diff
Binary file not shown.
+2908
-118
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -861,78 +861,78 @@ vio_ant_test u_vio_ant_test
|
||||
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
|
||||
);
|
||||
|
||||
// ila_rfcontrl u_ila_rfcontrl
|
||||
// (
|
||||
// .clk (clk_48m ), // input wire clk
|
||||
// .probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
||||
// .probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
||||
// .probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
||||
// .probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
||||
// .probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
||||
// .probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
||||
// .probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
||||
// .probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
||||
// .probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
||||
// .probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
||||
// .probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
||||
// .probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
||||
// .probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
||||
// .probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
||||
// .probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
||||
// .probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
||||
// .probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
||||
// .probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
||||
// .probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
||||
// .probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
||||
// .probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
||||
// .probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
||||
// .probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
||||
// .probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
||||
// .probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
||||
// .probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
||||
// .probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
||||
// .probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
||||
// .probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
||||
// .probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
||||
// .probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
||||
// .probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
||||
// .probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
||||
// .probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
||||
// .probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
||||
// .probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
||||
// .probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
||||
// .probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
||||
// .probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
||||
// .probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
||||
// .probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
||||
// .probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
||||
// .probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
||||
// .probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
||||
// .probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
||||
// .probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
||||
// .probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
||||
// .probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
||||
// .probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
||||
// .probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
||||
// );
|
||||
ila_rfcontrl u_ila_rfcontrl
|
||||
(
|
||||
.clk (clk_48m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
||||
.probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
||||
.probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
||||
.probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
||||
.probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
||||
.probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
||||
.probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
||||
.probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
||||
.probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
||||
.probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
||||
.probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
||||
.probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
||||
.probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
||||
.probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
||||
.probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
||||
.probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
||||
.probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
||||
.probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
||||
.probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
||||
.probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
||||
.probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
||||
.probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
||||
.probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
||||
.probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
||||
.probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
||||
.probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
||||
.probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
||||
.probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
||||
.probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
||||
.probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
||||
.probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
||||
.probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
||||
.probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
||||
.probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
||||
.probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
||||
.probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
||||
.probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
||||
.probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
||||
.probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
||||
.probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
||||
.probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
||||
.probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
||||
.probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
||||
.probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
||||
.probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
||||
.probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
||||
.probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
||||
.probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
||||
.probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
||||
.probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
||||
);
|
||||
|
||||
// ila_AntCtrl u_ila_AntCtrl
|
||||
// (
|
||||
// .clk (clk_96m ), // input wire clk
|
||||
// .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
||||
// .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
||||
// .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
||||
// .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
||||
// .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
||||
// .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
||||
// .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
||||
// .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
||||
// .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
// .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
// .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
||||
// .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
||||
// .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
||||
// );
|
||||
ila_AntCtrl u_ila_AntCtrl
|
||||
(
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
||||
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
||||
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
||||
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
||||
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
||||
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
||||
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
||||
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
||||
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
||||
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
||||
);
|
||||
|
||||
vio_rf_rd u_vio_rf_rd (
|
||||
.clk (clk_96m ), // input wire clk
|
||||
@@ -948,15 +948,15 @@ vio_rf_rd u_vio_rf_rd (
|
||||
.probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9
|
||||
);
|
||||
|
||||
// vio_ant_rd u_vio_ant_rd (
|
||||
// .clk (clk_96m ), // input wire clk
|
||||
// .probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
||||
// .probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
||||
// .probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
||||
// .probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
||||
// .probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
||||
// .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
|
||||
// );
|
||||
vio_ant_rd u_vio_ant_rd (
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
||||
.probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
||||
.probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
||||
.probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
||||
.probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
||||
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
|
||||
);
|
||||
|
||||
ila_2x12x1024 u_ila_tx
|
||||
(
|
||||
|
||||
Reference in New Issue
Block a user