diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/hdl/vio_v3_0_20_vio_include.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/hdl/vio_v3_0_20_vio_include.v deleted file mode 100644 index 0673f57f..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/hdl/vio_v3_0_20_vio_include.v +++ /dev/null @@ -1,283 +0,0 @@ -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) -`pragma protect key_block -GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx -XWe4lBDDrw== - -`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH -9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c -eVhT3XSIJDvufMyiJUc= - -`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit -pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX -LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 -5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a -sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== - -`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn -6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 -MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc -v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a -4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== - -`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v -ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX -cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC -xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa -draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv -j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO -R19uHYIhWP+7IpmjTiQ= - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM -kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV -cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 -7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 -mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) -`pragma protect data_block -vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm -QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc -F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ -lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi -PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM -O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri -OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1 -XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe -D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia -cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw -1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX -qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC -Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy -JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02 -vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb -Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta -ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf -+p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 -VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F -2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp -WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K -IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC -n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj 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All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. -`timescale 1ns / 1ps -module vio_hop ( -clk, - -probe_out0, -probe_out1 -); - -input clk; - -output reg [0 : 0] probe_out0 = 'h0 ; -output reg [0 : 0] probe_out1 = 'h0 ; - - -endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.veo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.veo deleted file mode 100644 index cd0f7803..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.veo +++ /dev/null @@ -1,67 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - -// IP VLNV: xilinx.com:ip:vio:3.0 -// IP Revision: 20 - -// The following must be inserted into your Verilog file for this -// core to be instantiated. Change the instance name and port connections -// (in parentheses) to your own signal names. - -//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -vio_hop your_instance_name ( - .clk(clk), // input wire clk - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1) // output wire [0 : 0] probe_out1 -); -// INST_TAG_END ------ End INSTANTIATION Template --------- - -// You must compile the wrapper file vio_hop.v when simulating -// the core, vio_hop. When compiling the wrapper file, be sure to -// reference the Verilog simulation library. - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.vho b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.vho deleted file mode 100644 index 1e2fb3d9..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop.vho +++ /dev/null @@ -1,79 +0,0 @@ --- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. --- --- This file contains confidential and proprietary information --- of Xilinx, Inc. and is protected under U.S. and --- international copyright and other intellectual property --- laws. --- --- DISCLAIMER --- This disclaimer is not a license and does not grant any --- rights to the materials distributed herewith. Except as --- otherwise provided in a valid license issued to you by --- Xilinx, and to the maximum extent permitted by applicable --- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --- (2) Xilinx shall not be liable (whether in contract or tort, --- including negligence, or under any other theory of --- liability) for any loss or damage of any kind or nature --- related to, arising under or in connection with these --- materials, including for any direct, or any indirect, --- special, incidental, or consequential loss or damage --- (including loss of data, profits, goodwill, or any type of --- loss or damage suffered as a result of any action brought --- by a third party) even if such damage or loss was --- reasonably foreseeable or Xilinx had been advised of the --- possibility of the same. --- --- CRITICAL APPLICATIONS --- Xilinx products are not designed or intended to be fail- --- safe, or for use in any application requiring fail-safe --- performance, such as life-support or safety devices or --- systems, Class III medical devices, nuclear facilities, --- applications related to the deployment of airbags, or any --- other applications that could lead to death, personal --- injury, or severe property or environmental damage --- (individually and collectively, "Critical --- Applications"). Customer assumes the sole risk and --- liability of any use of Xilinx products in Critical --- Applications, subject only to applicable laws and --- regulations governing limitations on product liability. --- --- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --- PART OF THIS FILE AT ALL TIMES. --- --- DO NOT MODIFY THIS FILE. - --- IP VLNV: xilinx.com:ip:vio:3.0 --- IP Revision: 20 - --- The following code must appear in the VHDL architecture header. - -------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT vio_hop - PORT ( - clk : IN STD_LOGIC; - probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) - ); -END COMPONENT; --- COMP_TAG_END ------ End COMPONENT Declaration ------------ - --- The following code must appear in the VHDL architecture --- body. Substitute your own instance name and net names. - -------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : vio_hop - PORT MAP ( - clk => clk, - probe_out0 => probe_out0, - probe_out1 => probe_out1 - ); --- INST_TAG_END ------ End INSTANTIATION Template --------- - --- You must compile the wrapper file vio_hop.vhd when simulating --- the core, vio_hop. When compiling the wrapper file, be sure to --- reference the VHDL simulation library. - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.v deleted file mode 100644 index bd2fe23f..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:0df86277ebb2f5544791c66610419aaae914fbe72ab918f95232817766eb0efc -size 300331 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.vhdl deleted file mode 100644 index a479e909..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:dd9e7e274f0c57e66147d3e987cee37bfd2370824dcd433d1c3b05df1b4238e5 -size 555415 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.vhdl deleted file mode 100644 index 754c0f7c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 19 12:04:19 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl --- Design : vio_hop --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_hop is - Port ( - clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end vio_hop; - -architecture stub of vio_hop is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v index d6016ee7..83468daf 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v @@ -48,7 +48,7 @@ `timescale 1ns / 1ps module vio_phase_comp ( clk, -probe_in0,probe_in1,probe_in2, +probe_in0,probe_in1, probe_out0, probe_out1, probe_out2, @@ -56,28 +56,21 @@ probe_out3, probe_out4, probe_out5, probe_out6, -probe_out7, -probe_out8, -probe_out9, -probe_out10 +probe_out7 ); input clk; input [31 : 0] probe_in0; input [0 : 0] probe_in1; -input [0 : 0] probe_in2; output reg [0 : 0] probe_out0 = 'h0 ; output reg [0 : 0] probe_out1 = 'h0 ; -output reg [11 : 0] probe_out2 = 'h000 ; -output reg [11 : 0] probe_out3 = 'h000 ; -output reg [11 : 0] probe_out4 = 'h000 ; -output reg [11 : 0] probe_out5 = 'h000 ; -output reg [11 : 0] probe_out6 = 'h000 ; -output reg [11 : 0] probe_out7 = 'h000 ; -output reg [11 : 0] probe_out8 = 'h000 ; -output reg [11 : 0] probe_out9 = 'h000 ; -output reg [4 : 0] probe_out10 = 'h09 ; +output reg [0 : 0] probe_out2 = 'h1 ; +output reg [0 : 0] probe_out3 = 'h0 ; +output reg [15 : 0] probe_out4 = 'h0000 ; +output reg [15 : 0] probe_out5 = 'h0000 ; +output reg [15 : 0] probe_out6 = 'h0000 ; +output reg [15 : 0] probe_out7 = 'h0000 ; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo index 59115898..befd1a65 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo @@ -55,21 +55,17 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG vio_phase_comp your_instance_name ( - .clk(clk), // input wire clk - .probe_in0(probe_in0), // input wire [31 : 0] probe_in0 - .probe_in1(probe_in1), // input wire [0 : 0] probe_in1 - .probe_in2(probe_in2), // input wire [0 : 0] probe_in2 - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 - .probe_out2(probe_out2), // output wire [11 : 0] probe_out2 - .probe_out3(probe_out3), // output wire [11 : 0] probe_out3 - .probe_out4(probe_out4), // output wire [11 : 0] probe_out4 - .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 - .probe_out6(probe_out6), // output wire [11 : 0] probe_out6 - .probe_out7(probe_out7), // output wire [11 : 0] probe_out7 - .probe_out8(probe_out8), // output wire [11 : 0] probe_out8 - .probe_out9(probe_out9), // output wire [11 : 0] probe_out9 - .probe_out10(probe_out10) // output wire [4 : 0] probe_out10 + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [31 : 0] probe_in0 + .probe_in1(probe_in1), // input wire [0 : 0] probe_in1 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [0 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [15 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [15 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [15 : 0] probe_out6 + .probe_out7(probe_out7) // output wire [15 : 0] probe_out7 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho index 3f3de6b8..5bbf64ad 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho @@ -57,18 +57,14 @@ COMPONENT vio_phase_comp clk : IN STD_LOGIC; probe_in0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_in2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out8 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out9 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -82,7 +78,6 @@ your_instance_name : vio_phase_comp clk => clk, probe_in0 => probe_in0, probe_in1 => probe_in1, - probe_in2 => probe_in2, probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, @@ -90,10 +85,7 @@ your_instance_name : vio_phase_comp probe_out4 => probe_out4, probe_out5 => probe_out5, probe_out6 => probe_out6, - probe_out7 => probe_out7, - probe_out8 => probe_out8, - probe_out9 => probe_out9, - probe_out10 => probe_out10 + probe_out7 => probe_out7 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v index 0b827f37..ab5fcf5a 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8997fdff3ed4d2114aaabee05c2bef90cf4fe526231cef8283afd1044c0026a2 -size 451591 +oid sha256:c54161de531f62c9b95a7d5c71ab9df4313489ff5f13778d75d6765db5339e9c +size 425691 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl index b5ac774c..efa6cc2d 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0bc5c8ddccfe953c1e56d33e0a0175daded79f5254373772e1e1e100db6755c9 -size 777511 +oid sha256:06d97b70737529844e27698b1b03e7a08b33b9958b620aa283bd7a6be042800f +size 736925 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v index 6b515e62..2a0bcfb0 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon Jun 12 15:47:42 2023 +// Date : Thu Jun 15 10:54:16 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -14,23 +14,18 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_out0, - probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, - probe_out9, probe_out10) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */; +module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */; input clk; input [31:0]probe_in0; input [0:0]probe_in1; - input [0:0]probe_in2; output [0:0]probe_out0; output [0:0]probe_out1; - output [11:0]probe_out2; - output [11:0]probe_out3; - output [11:0]probe_out4; - output [11:0]probe_out5; - output [11:0]probe_out6; - output [11:0]probe_out7; - output [11:0]probe_out8; - output [11:0]probe_out9; - output [4:0]probe_out10; + output [0:0]probe_out2; + output [0:0]probe_out3; + output [15:0]probe_out4; + output [15:0]probe_out5; + output [15:0]probe_out6; + output [15:0]probe_out7; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl index 71611359..60751ac0 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon Jun 12 15:47:42 2023 +-- Date : Thu Jun 15 10:54:16 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -17,18 +17,14 @@ entity vio_phase_comp is clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ) + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); end vio_phase_comp; @@ -37,7 +33,7 @@ architecture stub of vio_phase_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/README.txt deleted file mode 100644 index f3d66c82..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "ies", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/compile.do deleted file mode 100644 index d1641bc5..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib activehdl - -vlib activehdl/xil_defaultlib -vlib activehdl/xpm - -vmap xil_defaultlib activehdl/xil_defaultlib -vmap xpm activehdl/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"../../../ip/vio_hop/sim/vio_hop.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/file_info.txt deleted file mode 100644 index 89590acc..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/simulate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/simulate.do deleted file mode 100644 index cf34d258..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+vio_hop -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_hop xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {vio_hop.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/vio_hop.sh deleted file mode 100755 index b167f232..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/vio_hop.sh +++ /dev/null @@ -1,152 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Aldec Active-HDL Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - lib_map_path="" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/vio_hop.udo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/vio_hop.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/wave.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/activehdl/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/README.txt deleted file mode 100644 index f7601f7a..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/file_info.txt deleted file mode 100644 index 89590acc..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/run.f b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/run.f deleted file mode 100644 index 1d787daa..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib ies_lib/xil_defaultlib \ - "../../../ip/vio_hop/sim/vio_hop.v" \ --endlib --makelib ies_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/vio_hop.sh deleted file mode 100755 index f80f55ab..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/ies/vio_hop.sh +++ /dev/null @@ -1,177 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Cadence Incisive Enterprise Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="ies_lib" - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - irun $irun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_hop \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/vio_hop/hdl/verilog" \ - +incdir+"../../../ip/vio_hop/hdl" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/compile.do deleted file mode 100644 index 379e16ad..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/compile.do +++ /dev/null @@ -1,14 +0,0 @@ -vlib modelsim_lib/work -vlib modelsim_lib/msim - -vlib modelsim_lib/msim/xil_defaultlib - -vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib - -vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"../../../ip/vio_hop/sim/vio_hop.v" \ - - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/file_info.txt deleted file mode 100644 index d5ab2482..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/simulate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/simulate.do deleted file mode 100644 index 7a82b76e..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_hop xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure -view signals - -do {vio_hop.udo} - -run -all - -quit -force diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/vio_hop.sh deleted file mode 100755 index 57024f97..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/vio_hop.sh +++ /dev/null @@ -1,167 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Mentor Graphics ModelSim Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="modelsim_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/vio_hop.udo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/vio_hop.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/wave.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/modelsim/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/compile.do deleted file mode 100644 index d55d869e..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib questa_lib/work -vlib questa_lib/msim - -vlib questa_lib/msim/xil_defaultlib -vlib questa_lib/msim/xpm - -vmap xil_defaultlib questa_lib/msim/xil_defaultlib -vmap xpm questa_lib/msim/xpm - -vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"../../../ip/vio_hop/sim/vio_hop.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/elaborate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/elaborate.do deleted file mode 100644 index 13f19b1f..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/elaborate.do +++ /dev/null @@ -1 +0,0 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_hop xil_defaultlib.glbl -o vio_hop_opt diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/file_info.txt deleted file mode 100644 index 89590acc..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/simulate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/simulate.do deleted file mode 100644 index aaeb1823..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/simulate.do +++ /dev/null @@ -1,16 +0,0 @@ -onbreak {quit -f} -onerror {quit -f} - -vsim -t 1ps -lib xil_defaultlib vio_hop_opt - -do {wave.do} - -view wave -view structure -view signals - -do {vio_hop.udo} - -run -all - -quit -force diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/vio_hop.sh deleted file mode 100755 index 41e74ed6..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/vio_hop.sh +++ /dev/null @@ -1,174 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Mentor Graphics Questa Advanced Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -elaborate() -{ - source elaborate.do 2>&1 | tee -a elaborate.log -} - -# RUN_STEP: -simulate() -{ - vsim -64 -c -do "do {simulate.do}" -l simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Copy modelsim.ini file -copy_setup_file() -{ - file="modelsim.ini" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - cp $src_file . - fi -} - -# Create design library directory -create_lib_dir() -{ - lib_dir="questa_lib" - if [[ -e $lib_dir ]]; then - rm -rf $lib_dir - fi - - mkdir $lib_dir - -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/vio_hop.udo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/vio_hop.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/wave.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/questa/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/compile.do deleted file mode 100644 index a91698e7..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/compile.do +++ /dev/null @@ -1,22 +0,0 @@ -vlib work -vlib riviera - -vlib riviera/xil_defaultlib -vlib riviera/xpm - -vmap xil_defaultlib riviera/xil_defaultlib -vmap xpm riviera/xpm - -vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ - -vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ - -vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \ -"../../../ip/vio_hop/sim/vio_hop.v" \ - -vlog -work xil_defaultlib \ -"glbl.v" - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/file_info.txt deleted file mode 100644 index 89590acc..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/simulate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/simulate.do deleted file mode 100644 index cf34d258..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/simulate.do +++ /dev/null @@ -1,17 +0,0 @@ -onbreak {quit -force} -onerror {quit -force} - -asim -t 1ps +access +r +m+vio_hop -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_hop xil_defaultlib.glbl - -do {wave.do} - -view wave -view structure - -do {vio_hop.udo} - -run -all - -endsim - -quit -force diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/vio_hop.sh deleted file mode 100755 index a402bcb0..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/vio_hop.sh +++ /dev/null @@ -1,153 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Aldec Riviera-PRO Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - source compile.do 2>&1 | tee -a compile.log - -} - -# RUN_STEP: -simulate() -{ - runvsimsa -l simulate.log -do "do {simulate.do}" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - map_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - map_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Map library.cfg file -map_setup_file() -{ - file="library.cfg" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - vmap -link $lib_map_path - fi - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/vio_hop.udo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/vio_hop.udo deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/wave.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/wave.do deleted file mode 100644 index 70157b0c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/riviera/wave.do +++ /dev/null @@ -1,2 +0,0 @@ -add wave * -add wave /glbl/GSR diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/file_info.txt deleted file mode 100644 index d5ab2482..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/simulate.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/simulate.do deleted file mode 100644 index 58afc787..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/simulate.do +++ /dev/null @@ -1,2 +0,0 @@ -run -quit diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/vio_hop.sh deleted file mode 100755 index 60db7bde..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/vcs/vio_hop.sh +++ /dev/null @@ -1,221 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Synopsys Verilog Compiler Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Command line options -vlogan_opts="-full64" -vhdlan_opts="-full64" -vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" -vcs_sim_opts="-ucli -licqueue -l simulate.log" - -# Design libraries -design_libs=(xil_defaultlib) - -# Simulation root library directory -sim_lib_dir="vcs_lib" - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_hop/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_hop/hdl" \ - "$ref_dir/../../../ip/vio_hop/sim/vio_hop.v" \ - 2>&1 | tee -a vlogan.log - - - vlogan -work xil_defaultlib $vlogan_opts +v2k \ - glbl.v \ - 2>&1 | tee -a vlogan.log - -} - -# RUN_STEP: -elaborate() -{ - vcs $vcs_elab_opts xil_defaultlib.vio_hop xil_defaultlib.glbl -o vio_hop_simv -} - -# RUN_STEP: -simulate() -{ - ./vio_hop_simv $vcs_sim_opts -do simulate.do -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - create_lib_mappings $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - create_lib_mappings $2 - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Define design library mappings -create_lib_mappings() -{ - file="synopsys_sim.setup" - if [[ -e $file ]]; then - if [[ ($1 == "") ]]; then - return - else - rm -rf $file - fi - fi - - touch $file - - if [[ ($1 != "") ]]; then - lib_map_path="$1" - else - lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - mapping="$lib:$sim_lib_dir/$lib" - echo $mapping >> $file - done - - if [[ ($lib_map_path != "") ]]; then - incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" - echo $incl_ref >> $file - fi -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(ucli.key vio_hop_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_hop_simv.daidir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/README.txt deleted file mode 100644 index f7601f7a..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/README.txt +++ /dev/null @@ -1,48 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'execute' function for the single-step flow. This -function is called from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/file_info.txt deleted file mode 100644 index 89590acc..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/file_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/run.f b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/run.f deleted file mode 100644 index 7f6bb6ab..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/run.f +++ /dev/null @@ -1,14 +0,0 @@ --makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ --endlib --makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - "../../../ip/vio_hop/sim/vio_hop.v" \ --endlib --makelib xcelium_lib/xil_defaultlib \ - glbl.v --endlib - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/vio_hop.sh deleted file mode 100755 index 79fe342b..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xcelium/vio_hop.sh +++ /dev/null @@ -1,177 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Cadence Xcelium Parallel Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the -# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the -# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch -# that points to these libraries and rerun export_simulation. For more information about this switch please -# type 'export_simulation -help' in the Tcl shell. -# -# You can also point to the simulation libraries by either replacing the in this -# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_hop.sh -help' for more information. -# -# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' -# -#********************************************************************************************************* - -# Directory path for design sources and include directories (if any) wrt this path -ref_dir="." - -# Override directory with 'export_sim_ref_dir' env path value if set in the shell -if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then - ref_dir="$export_sim_ref_dir" -fi - -# Set the compiled library directory -ref_lib_dir="." - -# Command line options -xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" - -# Design libraries -design_libs=(xil_defaultlib xpm) - -# Simulation root library directory -sim_lib_dir="xcelium_lib" - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - execute -} - -# RUN_STEP: -execute() -{ - xrun $xrun_opts \ - -reflib "$ref_lib_dir/unisim:unisim" \ - -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ - -reflib "$ref_lib_dir/secureip:secureip" \ - -reflib "$ref_lib_dir/unimacro:unimacro" \ - -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_hop \ - -f run.f \ - -top glbl \ - glbl.v \ - +incdir+"../../../ip/vio_hop/hdl/verilog" \ - +incdir+"../../../ip/vio_hop/hdl" -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - else - ref_lib_dir=$2 - fi - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - esac - - create_lib_dir - - # Add any setup/initialization commands here:- - - # - -} - -# Create design library directory paths -create_lib_dir() -{ - if [[ -e $sim_lib_dir ]]; then - rm -rf $sim_lib_dir - fi - - for (( i=0; i<${#design_libs[*]}; i++ )); do - lib="${design_libs[i]}" - lib_dir="$sim_lib_dir/$lib" - if [[ ! -e $lib_dir ]]; then - mkdir -p $lib_dir - fi - done -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done - - create_lib_dir -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/README.txt deleted file mode 100644 index 35621b64..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/README.txt +++ /dev/null @@ -1,49 +0,0 @@ -################################################################################ -# Vivado (TM) v2019.1.3 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required to -# run the exported script and information about the source files. -# -# Generated by export_simulation on Wed Apr 19 12:04:01 CST 2023 -# -################################################################################ - -1. How to run the generated simulation script:- - -From the shell prompt in the current directory, issue the following command:- - -./vio_hop.sh - -This command will launch the 'compile', 'elaborate' and 'simulate' functions -implemented in the script file for the 3-step flow. These functions are called -from the main 'run' function in the script file. - -The 'run' function first executes the 'setup' function, the purpose of which is to -create simulator specific setup files, create design library mappings and library -directories and copy 'glbl.v' from the Vivado software install location into the -current directory. - -The 'setup' function is also used for removing the simulator generated data in -order to reset the current directory to the original state when export_simulation -was launched from Vivado. This generated data can be removed by specifying the -'-reset_run' switch to the './vio_hop.sh' script. - -./vio_hop.sh -reset_run - -To keep the generated data from the previous run but regenerate the setup files and -library directories, use the '-noclean_files' switch. - -./vio_hop.sh -noclean_files - -For more information on the script, please type './vio_hop.sh -help'. - -2. Additional design information files:- - -export_simulation generates following additional file that can be used for fetching -the design files information or for integrating with external custom scripts. - -Name : file_info.txt -Purpose: This file contains detail design file information based on the compile order - when export_simulation was executed from Vivado. The file contains information - about the file type, name, whether it is part of the IP, associated library - and the file path information. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/cmd.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/cmd.tcl deleted file mode 100644 index eef7a0f0..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/cmd.tcl +++ /dev/null @@ -1,12 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run -all -quit diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/file_info.txt deleted file mode 100644 index d5ab2482..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/file_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -vio_hop.v,verilog,xil_defaultlib,../../../ip/vio_hop/sim/vio_hop.v,incdir="../../../ip/vio_hop/hdl/verilog"incdir="../../../ip/vio_hop/hdl" -glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/glbl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/glbl.v deleted file mode 100644 index be642335..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vio_hop.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vio_hop.sh deleted file mode 100755 index 799ca3e0..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vio_hop.sh +++ /dev/null @@ -1,212 +0,0 @@ -#!/bin/bash -f -#********************************************************************************************************* -# Vivado (TM) v2019.1.3 (64-bit) -# -# Filename : vio_hop.sh -# Simulator : Xilinx Vivado Simulator -# Description : Simulation script for compiling, elaborating and verifying the project source files. -# The script will automatically create the design libraries sub-directories in the run -# directory, add the library logical mappings in the simulator setup file, create default -# 'do/prj' file, execute compilation, elaboration and simulation steps. -# -# Generated by Vivado on Wed Apr 19 12:04:01 CST 2023 -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# -# usage: vio_hop.sh [-help] -# usage: vio_hop.sh [-lib_map_path] -# usage: vio_hop.sh [-noclean_files] -# usage: vio_hop.sh [-reset_run] -# -#********************************************************************************************************* - -# Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 -xvlog_opts="--relax" - - -# Script info -echo -e "vio_hop.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" - -# Main steps -run() -{ - check_args $# $1 - setup $1 $2 - compile - elaborate - simulate -} - -# RUN_STEP: -compile() -{ - # Compile design files - xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log - -} - -# RUN_STEP: -elaborate() -{ - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_hop xil_defaultlib.vio_hop xil_defaultlib.glbl -log elaborate.log -} - -# RUN_STEP: -simulate() -{ - xsim vio_hop -key {Behavioral:sim_1:Functional:vio_hop} -tclbatch cmd.tcl -log simulate.log -} - -# STEP: setup -setup() -{ - case $1 in - "-lib_map_path" ) - if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - copy_setup_file $2 - ;; - "-reset_run" ) - reset_run - echo -e "INFO: Simulation run files deleted.\n" - exit 0 - ;; - "-noclean_files" ) - # do not remove previous data - ;; - * ) - copy_setup_file $2 - esac - - # Add any setup/initialization commands here:- - - # - -} - -# Copy xsim.ini file -copy_setup_file() -{ - file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" - if [[ ($1 != "") ]]; then - lib_map_path="$1" - fi - if [[ ($lib_map_path != "") ]]; then - src_file="$lib_map_path/$file" - if [[ -e $src_file ]]; then - cp $src_file . - fi - - # Map local design libraries to xsim.ini - map_local_libs - - fi -} - -# Map local design libraries -map_local_libs() -{ - updated_mappings=() - local_mappings=() - - # Local design libraries - local_libs=() - - if [[ 0 == ${#local_libs[@]} ]]; then - return - fi - - file="xsim.ini" - file_backup="xsim.ini.bak" - - if [[ -e $file ]]; then - rm -f $file_backup - # Create a backup copy of the xsim.ini file - cp $file $file_backup - # Read libraries from backup file and search in local library collection - while read -r line - do - IN=$line - # Split mapping entry with '=' delimiter to fetch library name and mapping - read lib_name mapping <<<$(IFS="="; echo $IN) - # If local library found, then construct the local mapping and add to local mapping collection - if `echo ${local_libs[@]} | grep -wq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - local_mappings+=("$lib_name") - fi - # Add to updated library mapping collection - updated_mappings+=("$line") - done < "$file_backup" - # Append local libraries not found originally from xsim.ini - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then - line="$lib_name=xsim.dir/$lib_name" - updated_mappings+=("$line") - fi - done - # Write updated mappings in xsim.ini - rm -f $file - for (( i=0; i<${#updated_mappings[*]}; i++ )); do - lib_name="${updated_mappings[i]}" - echo $lib_name >> $file - done - else - for (( i=0; i<${#local_libs[*]}; i++ )); do - lib_name="${local_libs[i]}" - mapping="$lib_name=xsim.dir/$lib_name" - echo $mapping >> $file - done - fi -} - -# Delete generated data from the previous run -reset_run() -{ - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_hop.wdb xsim.dir) - for (( i=0; i<${#files_to_remove[*]}; i++ )); do - file="${files_to_remove[i]}" - if [[ -e $file ]]; then - rm -rf $file - fi - done -} - -# Check command line arguments -check_args() -{ - if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_hop.sh -help\" for more information)\n" - exit 1 - fi - - if [[ ($2 == "-help" || $2 == "-h") ]]; then - usage - fi -} - -# Script usage -usage() -{ - msg="Usage: vio_hop.sh [-help]\n\ -Usage: vio_hop.sh [-lib_map_path]\n\ -Usage: vio_hop.sh [-reset_run]\n\ -Usage: vio_hop.sh [-noclean_files]\n\n\ -[-help] -- Print help information for this script\n\n\ -[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ -using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ -[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ -from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ --noclean_files switch.\n\n\ -[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" - echo -e $msg - exit 1 -} - -# Launch script -run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vlog.prj b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vlog.prj deleted file mode 100644 index 1312dac9..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_hop/xsim/vlog.prj +++ /dev/null @@ -1,6 +0,0 @@ -verilog xil_defaultlib --include "../../../ip/vio_hop/hdl/verilog" --include "../../../ip/vio_hop/hdl" \ -"../../../ip/vio_hop/sim/vio_hop.v" \ - -verilog xil_defaultlib "glbl.v" - -nosort diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh index 442e7f2f..d223ae8f 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt index 38658a26..f116af74 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh index 999ef6ea..d74cfbde 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh index 5c895255..f2e6683c 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh index 78190b4a..6738f0b4 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh index 5907360a..7fdd6f28 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh index 49d8560e..482c03df 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt index 38658a26..f116af74 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh index 4a819a43..23c979de 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt index 07ce2ac8..703b82e1 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023 +# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh index 989ff860..b7d777ef 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023 +# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/0ddc3e874811cad5.xci b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/0ddc3e874811cad5.xci new file mode 100644 index 00000000..994ff489 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/0ddc3e874811cad5.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 0ddc3e874811cad5 + 0 + + + vio_phase_comp + + + 100000000 + 1 + 1 + 2 + 8 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 000000000000 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x000 + 12 + vio_phase_comp + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 0ddc3e874811cad5 + 9a10a187 + 14 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp.dcp new file mode 100644 index 00000000..312ecbeb --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f56b954d51dea353fd9d4a16c40cd3eff25ff0c8e1a98b6edc662d940f28938b +size 180818 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.v new file mode 100755 index 00000000..4f140576 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:58785c0f7c6ba024f5102a2369c0cbd0ec3e4736a1353c05b88e3cfd5195bf68 +size 426110 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.vhdl new file mode 100755 index 00000000..33ef936e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:648fe8311b188d0c805fe90a63cb3f0483408df82fd8cb455be244dd93dd52e5 +size 773633 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.v old mode 100644 new mode 100755 similarity index 50% rename from projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.v rename to projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.v index c4a7f480..857e7886 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop/vio_hop_stub.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.v @@ -1,11 +1,11 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 19 12:04:19 2023 +// Date : Thu Jun 15 10:54:16 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v -// Design : vio_hop +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v +// Design : vio_phase_comp // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 // -------------------------------------------------------------------------------- @@ -14,9 +14,18 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_hop(clk, probe_out0, probe_out1) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0]" */; +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */; input clk; + input [31:0]probe_in0; + input [0:0]probe_in1; output [0:0]probe_out0; output [0:0]probe_out1; + output [0:0]probe_out2; + output [0:0]probe_out3; + output [15:0]probe_out4; + output [15:0]probe_out5; + output [15:0]probe_out6; + output [15:0]probe_out7; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.vhdl new file mode 100755 index 00000000..478c7c85 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0ddc3e874811cad5/vio_phase_comp_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Jun 15 10:54:16 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/df222aafb45b4438.xci b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/df222aafb45b4438.xci new file mode 100644 index 00000000..8e3b0236 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/df222aafb45b4438.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + df222aafb45b4438 + 0 + + + vio_phase_comp + + + 100000000 + 1 + 1 + 3 + 13 + 32 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 000000000000 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x000 + 12 + vio_phase_comp + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + df222aafb45b4438 + 9a10a187 + 14 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp.dcp new file mode 100644 index 00000000..6e981192 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:98cfcb4bf1e6507114fd1a859e5323c01101982d7a285e06685ea8a95f147314 +size 202627 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.v new file mode 100755 index 00000000..a4d7ad4e --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:48737e19571f446f6c740b40975c2fa6f5de0a621491283607164d3c1d870e9e +size 461456 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.vhdl new file mode 100755 index 00000000..b088bc2c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e0af54e25a59c5d278c30e655672f259a9ac5e4ce399eb354ec6a4a8b2033bad +size 825472 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.v new file mode 100755 index 00000000..5385bfe4 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.v @@ -0,0 +1,38 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed Jun 14 18:26:11 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v +// Design : vio_phase_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0],probe_out11[0:0],probe_out12[0:0]" */; + input clk; + input [31:0]probe_in0; + input [0:0]probe_in1; + input [0:0]probe_in2; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [11:0]probe_out2; + output [11:0]probe_out3; + output [11:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [11:0]probe_out7; + output [11:0]probe_out8; + output [11:0]probe_out9; + output [4:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; +endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.vhdl new file mode 100755 index 00000000..8b76ff4a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/df222aafb45b4438/vio_phase_comp_stub.vhdl @@ -0,0 +1,46 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed Jun 14 18:26:11 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0],probe_out11[0:0],probe_out12[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 346b1ea8..d50d0e71 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,10 +1,10 @@ version:1 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-70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313337:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313437:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:31:00:00 @@ -21,9 +21,9 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636f70795f6970:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3230:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3232:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:39:00:00 -eof:1997016473 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:3131:00:00 +eof:2845626422 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 8476720c..9b6b7ccb 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -3,10 +3,10 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:39:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:33:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:37:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:38:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:39:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3237:00:00 -eof:976246183 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3330:00:00 +eof:885397058 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index f16dd141..75df9a5f 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:16 +6d6f64655f636f756e7465727c4755494d6f6465:18 eof: diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index a9e510e3..6de04bd4 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -34,6 +34,6 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323038362e3136304d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638332e3237374d42:00:00 -eof:1830882776 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323038332e3139314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638302e3330394d42:00:00 +eof:1838207814 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 4303aa17..68c3f126 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -21,20 +21,20 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - - + + - + @@ -51,16 +51,16 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - + - +
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml new file mode 100644 index 00000000..7aae5b27 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml new file mode 100644 index 00000000..7aae5b27 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.Vivado_Synthesis.queue.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst deleted file mode 100644 index c4cc8a9e..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.end.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.end.rst deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.js b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.js deleted file mode 100755 index 3e83de11..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.js +++ /dev/null @@ -1,270 +0,0 @@ -// -// Vivado(TM) -// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 -// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. -// - -// GLOBAL VARIABLES -var ISEShell = new ActiveXObject( "WScript.Shell" ); -var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); -var ISERunDir = ""; -var ISELogFile = "runme.log"; -var ISELogFileStr = null; -var ISELogEcho = true; -var ISEOldVersionWSH = false; - - - -// BOOTSTRAP -ISEInit(); - - - -// -// ISE FUNCTIONS -// -function ISEInit() { - - // 1. RUN DIR setup - var ISEScrFP = WScript.ScriptFullName; - var ISEScrN = WScript.ScriptName; - ISERunDir = - ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); - - // 2. LOG file setup - ISELogFileStr = ISEOpenFile( ISELogFile ); - - // 3. LOG echo? - var ISEScriptArgs = WScript.Arguments; - for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; - ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); - ISELogFileStr = ISEOpenFile( ISELogFile ); - - } else { // WSH 5.6 - - // LAUNCH! - ISEShell.CurrentDirectory = ISERunDir; - - // Redirect STDERR to STDOUT - ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; - var ISEProcess = ISEShell.Exec( ISECmdLine ); - - // BEGIN file creation - var wbemFlagReturnImmediately = 0x10; - var wbemFlagForwardOnly = 0x20; - var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); - var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); - var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); - var NOC = 0; - var NOLP = 0; - var TPM = 0; - - var cpuInfos = new Enumerator(processor); - for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { - var cpuInfo = cpuInfos.item(); - NOC += cpuInfo.NumberOfCores; - NOLP += cpuInfo.NumberOfLogicalProcessors; - } - var csInfos = new Enumerator(computerSystem); - for(;!csInfos.atEnd(); csInfos.moveNext()) { - var csInfo = csInfos.item(); - TPM += csInfo.TotalPhysicalMemory; - } - - var ISEHOSTCORE = NOLP - var ISEMEMTOTAL = TPM - - var ISENetwork = WScript.CreateObject( "WScript.Network" ); - var ISEHost = ISENetwork.ComputerName; - var ISEUser = ISENetwork.UserName; - var ISEPid = ISEProcess.ProcessID; - var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( " " ); - ISEBeginFile.WriteLine( "" ); - ISEBeginFile.Close(); - - var ISEOutStr = ISEProcess.StdOut; - var ISEErrStr = ISEProcess.StdErr; - - // WAIT for ISEStep to finish - while ( ISEProcess.Status == 0 ) { - - // dump stdout then stderr - feels a little arbitrary - while ( !ISEOutStr.AtEndOfStream ) { - ISEStdOut( ISEOutStr.ReadLine() ); - } - - WScript.Sleep( 100 ); - } - - ISEExitCode = ISEProcess.ExitCode; - } - - ISELogFileStr.Close(); - - // END/ERROR file creation - if ( ISEExitCode != 0 ) { - ISETouchFile( ISEStep, "error" ); - - } else { - ISETouchFile( ISEStep, "end" ); - } - - return ISEExitCode; -} - - -// -// UTILITIES -// -function ISEStdOut( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdOut.WriteLine( ISELine ); - } -} - -function ISEStdErr( ISELine ) { - - ISELogFileStr.WriteLine( ISELine ); - - if ( ISELogEcho ) { - WScript.StdErr.WriteLine( ISELine ); - } -} - -function ISETouchFile( ISERoot, ISEStatus ) { - - var ISETFile = - ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); - ISETFile.Close(); -} - -function ISEOpenFile( ISEFilename ) { - - // This function has been updated to deal with a problem seen in CR #870871. - // In that case the user runs a script that runs impl_1, and then turns around - // and runs impl_1 -to_step write_bitstream. That second run takes place in - // the same directory, which means we may hit some of the same files, and in - // particular, we will open the runme.log file. Even though this script closes - // the file (now), we see cases where a subsequent attempt to open the file - // fails. Perhaps the OS is slow to release the lock, or the disk comes into - // play? In any case, we try to work around this by first waiting if the file - // is already there for an arbitrary 5 seconds. Then we use a try-catch block - // and try to open the file 10 times with a one second delay after each attempt. - // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. - // If there is an unrecognized exception when trying to open the file, we output - // an error message and write details to an exception.log file. - var ISEFullPath = ISERunDir + "/" + ISEFilename; - if (ISEFileSys.FileExists(ISEFullPath)) { - // File is already there. This could be a problem. Wait in case it is still in use. - WScript.Sleep(5000); - } - var i; - for (i = 0; i < 10; ++i) { - try { - return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); - } catch (exception) { - var error_code = exception.number & 0xFFFF; // The other bits are a facility code. - if (error_code == 52) { // 52 is bad file name or number. - // Wait a second and try again. - WScript.Sleep(1000); - continue; - } else { - WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - var exceptionFilePath = ISERunDir + "/exception.log"; - if (!ISEFileSys.FileExists(exceptionFilePath)) { - WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); - var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); - exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); - exceptionFile.WriteLine("\tException name: " + exception.name); - exceptionFile.WriteLine("\tException error code: " + error_code); - exceptionFile.WriteLine("\tException message: " + exception.message); - exceptionFile.Close(); - } - throw exception; - } - } - } - // If we reached this point, we failed to open the file after 10 attempts. - // We need to error out. - WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); - WScript.Quit(1); -} diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.sh deleted file mode 100755 index f679f2e8..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/ISEWrap.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# ISEWrap.sh: Vivado Runs Script for UNIX -# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -# - -HD_LOG=$1 -shift - -# CHECK for a STOP FILE -if [ -f .stop.rst ] -then -echo "" >> $HD_LOG -echo "*** Halting run - EA reset detected ***" >> $HD_LOG -echo "" >> $HD_LOG -exit 1 -fi - -ISE_STEP=$1 -shift - -# WRITE STEP HEADER to LOG -echo "" >> $HD_LOG -echo "*** Running $ISE_STEP" >> $HD_LOG -echo " with args $@" >> $HD_LOG -echo "" >> $HD_LOG - -# LAUNCH! -$ISE_STEP "$@" >> $HD_LOG 2>&1 & - -# BEGIN file creation -ISE_PID=$! -if [ X != X$HOSTNAME ] -then -ISE_HOST=$HOSTNAME #bash -else -ISE_HOST=$HOST #csh -fi -ISE_USER=$USER - -ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) -ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) - -ISE_BEGINFILE=.$ISE_STEP.begin.rst -/bin/touch $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo " " >> $ISE_BEGINFILE -echo "" >> $ISE_BEGINFILE - -# WAIT for ISEStep to finish -wait $ISE_PID - -# END/ERROR file creation -RETVAL=$? -if [ $RETVAL -eq 0 ] -then - /bin/touch .$ISE_STEP.end.rst -else - /bin/touch .$ISE_STEP.error.rst -fi - -exit $RETVAL - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/__synthesis_is_complete__ deleted file mode 100644 index e69de29b..00000000 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml deleted file mode 100644 index 1822c528..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml +++ /dev/null @@ -1,59 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/htr.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/htr.txt deleted file mode 100644 index 882c0207..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Vivado(TM) -# htr.txt: a Vivado-generated description of how-to-repeat the -# the basic steps of a run. Note that runme.bat/sh needs -# to be invoked for Vivado to track run status. -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -vivado -log vio_hop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_hop.tcl diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf deleted file mode 100644 index 76684d54..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf +++ /dev/null @@ -1,38 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f686f70:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3131:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3131:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:47557159 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/rundef.js b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/rundef.js deleted file mode 100644 index 948a28a3..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/rundef.js +++ /dev/null @@ -1,40 +0,0 @@ -// -// Vivado(TM) -// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; -} else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - "-log vio_hop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_hop.tcl" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.bat b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.bat deleted file mode 100644 index ba55218d..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.bat +++ /dev/null @@ -1,11 +0,0 @@ -@echo off - -rem Vivado (TM) -rem runme.bat: a Vivado-generated Script -rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.sh deleted file mode 100755 index c1f9d38a..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/runme.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# runme.sh: a Vivado-generated Runs Script for UNIX -# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin -else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1' -cd "$HD_PWD" - -HD_LOG=runme.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrap.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -log vio_hop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_hop.tcl diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp deleted file mode 100644 index 46488d4c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:6239eab20b0346c7321a40d4e879edbddffcb80c6957e8466a61e5b6ddf57650 -size 112135 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.tcl deleted file mode 100644 index 5a18bfcd..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.tcl +++ /dev/null @@ -1,155 +0,0 @@ -# -# Synthesis run script generated by Vivado -# - -set TIME_start [clock seconds] -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin -set_param project.vivado.isBlockSynthRun true -set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 - -set_param project.singleFileAddWarning.threshold 0 -set_param project.compositeFile.enableAutoGeneration 0 -set_param synth.vivado.isSynthRun true -set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr [current_project] -set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] -set_property default_lib xil_defaultlib [current_project] -set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] -set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop_ooc.xdc] - -# Mark all dcp files as not used in implementation to prevent them from being -# stitched into the results of this synthesis run. Any black boxes in the -# design are intentionally left as such for best results. Dcp files will be -# stitched into the design at a later time, either when this synthesis run is -# opened, or when it is stitched into a dependent implementation run. -foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { - set_property used_in_implementation false $dcp -} -set_param ips.enableIPCacheLiteLoad 1 - -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1 -new_name vio_hop -ip [get_ips vio_hop]] - -if { $cached_ip eq {} } { -close [open __synthesis_is_running__ w] - -synth_design -top vio_hop -part xc7k410tffg900-2 -mode out_of_context - -#--------------------------------------------------------- -# Generate Checkpoint/Stub/Simulation Files For IP Cache -#--------------------------------------------------------- -# disable binary constraint mode for IPCache checkpoints -set_param constraints.enableBinaryConstraints false - -catch { - write_checkpoint -force -noxdef -rename_prefix vio_hop_ vio_hop.dcp - - set ipCachedFiles {} - write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_hop_stub.v - lappend ipCachedFiles vio_hop_stub.v - - write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_hop_stub.vhdl - lappend ipCachedFiles vio_hop_stub.vhdl - - write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_hop_sim_netlist.v - lappend ipCachedFiles vio_hop_sim_netlist.v - - write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_hop_sim_netlist.vhdl - lappend ipCachedFiles vio_hop_sim_netlist.vhdl -set TIME_taken [expr [clock seconds] - $TIME_start] - - config_ip_cache -add -dcp vio_hop.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_hop] -} - -rename_ref -prefix_all vio_hop_ - -# disable binary constraint mode for synth run checkpoints -set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef vio_hop.dcp -create_report "vio_hop_synth_1_synth_report_utilization_0" "report_utilization -file vio_hop_utilization_synth.rpt -pb vio_hop_utilization_synth.pb" - -if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" -} - -if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - -if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl -} _RESULT ] } { - puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" -} - - -} else { - - -}; # end if cached_ip - -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci] - -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci] - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop - } -} - -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop]} { - catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_hop - } -} -file delete __synthesis_is_running__ -close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.vds b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.vds deleted file mode 100644 index 3c5c345c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.vds +++ /dev/null @@ -1,508 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2019.1.3 (64-bit) -# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 -# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Apr 19 12:04:02 2023 -# Process ID: 1956410 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1 -# Command line: vivado -log vio_hop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_hop.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vivado.jou -#----------------------------------------------------------- -source vio_hop.tcl -notrace -Command: synth_design -top vio_hop -part xc7k410tffg900-2 -mode out_of_context -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1956494 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1830.469 ; gain = 153.719 ; free physical = 2080 ; free virtual = 42827 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_hop' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/synth/vio_hop.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_hop does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/synth/vio_hop.v:73] -INFO: [Synth 8-6155] done synthesizing module 'vio_hop' (6#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/synth/vio_hop.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in53[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in54[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in55[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in56[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in57[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in58[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in64[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in65[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in66[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in67[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in68[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in69[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in70[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in71[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in72[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in73[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in74[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in75[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in76[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in77[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in78[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in79[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in80[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in81[0] -INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1892.156 ; gain = 215.406 ; free physical = 2098 ; free virtual = 42851 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.125 ; gain = 218.375 ; free physical = 2091 ; free virtual = 42851 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.125 ; gain = 218.375 ; free physical = 2091 ; free virtual = 42851 ---------------------------------------------------------------------------------- -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop_ooc.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop_ooc.xdc] -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xdc] -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2053.812 ; gain = 0.000 ; free physical = 1945 ; free virtual = 42722 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2062.719 ; gain = 8.906 ; free physical = 1945 ; free virtual = 42722 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 2009 ; free virtual = 42798 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 2009 ; free virtual = 42798 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 2009 ; free virtual = 42798 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 2000 ; free virtual = 42792 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Registers : - 128 Bit Registers := 1 - 16 Bit Registers := 8 - 7 Bit Registers := 1 - 5 Bit Registers := 1 - 3 Bit Registers := 2 - 1 Bit Registers := 17 -+---Muxes : - 2 Input 16 Bit Muxes := 3 - 2 Input 1 Bit Muxes := 8 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- -Hierarchical RTL Component report -Module vio_v3_0_20_probe_out_one -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_probe_out_all -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 5 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 2 -Module xsdbs_v1_0_2_xsdbs -Detailed RTL Component Info : -+---Registers : - 128 Bit Registers := 1 - 16 Bit Registers := 2 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 1 -Module vio_v3_0_20_decoder -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 2 - 7 Bit Registers := 1 - 5 Bit Registers := 1 - 3 Bit Registers := 2 - 1 Bit Registers := 9 -+---Muxes : - 2 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 3 -Module vio_v3_0_20_vio -Detailed RTL Component Info : -+---Registers : - 16 Bit Registers := 1 ---------------------------------------------------------------------------------- -Finished RTL Hierarchical Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[1]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[2]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[3]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[4]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[5]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[6]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[7]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[8]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[9]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[10]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[11]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[12]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[13]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[14]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15] ) ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1971 ; free virtual = 42802 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1785 ; free virtual = 42684 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1784 ; free virtual = 42684 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1778 ; free virtual = 42678 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 -WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- - -Report Check Netlist: -+------+------------------+-------+---------+-------+------------------+ -| |Item |Errors |Warnings |Status |Description | -+------+------------------+-------+---------+-------+------------------+ -|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | -+------+------------------+-------+---------+-------+------------------+ ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- - -Report RTL Partitions: -+-+--------------+------------+----------+ -| |RTL Partition |Replication |Instances | -+-+--------------+------------+----------+ -+-+--------------+------------+----------+ ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT2 | 2| -|2 |LUT3 | 26| -|3 |LUT4 | 21| -|4 |LUT5 | 13| -|5 |LUT6 | 58| -|6 |FDRE | 234| -+------+-----+------+ - -Report Instance Areas: -+------+---------------------------------------+----------------------------+------+ -| |Instance |Module |Cells | -+------+---------------------------------------+----------------------------+------+ -|1 |top | | 354| -|2 | inst |vio_v3_0_20_vio | 354| -|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 72| -|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 18| -|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| -|7 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| -+------+---------------------------------------+----------------------------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1763 ; free virtual = 42674 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2062.719 ; gain = 218.375 ; free physical = 1816 ; free virtual = 42728 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2062.719 ; gain = 385.969 ; free physical = 1816 ; free virtual = 42728 -INFO: [Project 1-571] Translating synthesized netlist -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2065.688 ; gain = 0.000 ; free physical = 1742 ; free virtual = 42659 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Common 17-83] Releasing license: Synthesis -58 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2065.688 ; gain = 666.770 ; free physical = 1835 ; free virtual = 42751 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2065.688 ; gain = 0.000 ; free physical = 1835 ; free virtual = 42751 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp' has been generated. -WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_hop, cache-ID = 9e6e674e15ee48e5 -INFO: [Coretcl 2-1174] Renamed 6 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.699 ; gain = 0.000 ; free physical = 1827 ; free virtual = 42756 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file vio_hop_utilization_synth.rpt -pb vio_hop_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed Apr 19 12:04:19 2023... diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v deleted file mode 100644 index bd2fe23f..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:0df86277ebb2f5544791c66610419aaae914fbe72ab918f95232817766eb0efc -size 300331 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl deleted file mode 100644 index a479e909..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:dd9e7e274f0c57e66147d3e987cee37bfd2370824dcd433d1c3b05df1b4238e5 -size 555415 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v deleted file mode 100644 index c4a7f480..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v +++ /dev/null @@ -1,22 +0,0 @@ -// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 19 12:04:19 2023 -// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v -// Design : vio_hop -// Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_hop(clk, probe_out0, probe_out1) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0]" */; - input clk; - output [0:0]probe_out0; - output [0:0]probe_out1; -endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl deleted file mode 100644 index 754c0f7c..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl +++ /dev/null @@ -1,32 +0,0 @@ --- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 19 12:04:19 2023 --- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl --- Design : vio_hop --- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity vio_hop is - Port ( - clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - -end vio_hop; - -architecture stub of vio_hop is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; -begin -end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.pb deleted file mode 100644 index 1df29166..00000000 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.pb and /dev/null differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.rpt deleted file mode 100644 index 3863b004..00000000 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_utilization_synth.rpt +++ /dev/null @@ -1,178 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Wed Apr 19 12:04:19 2023 -| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -| Command : report_utilization -file vio_hop_utilization_synth.rpt -pb vio_hop_utilization_synth.pb -| Design : vio_hop -| Device : 7k410tffg900-2 -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Memory -3. DSP -4. IO and GT Specific -5. Clocking -6. Specific Feature -7. Primitives -8. Black Boxes -9. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 100 | 0 | 254200 | 0.04 | -| LUT as Logic | 100 | 0 | 254200 | 0.04 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 234 | 0 | 508400 | 0.05 | -| Register as Flip Flop | 234 | 0 | 508400 | 0.05 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | -+-------------------------+------+-------+-----------+-------+ -* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 234 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Memory ---------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| Block RAM Tile | 0 | 0 | 795 | 0.00 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 0 | 0 | 1590 | 0.00 | -+----------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -3. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -4. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | -| Bonded IPADs | 0 | 0 | 50 | 0.00 | -| Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -5. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -6. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -7. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| FDRE | 234 | Flop & Latch | -| LUT6 | 58 | LUT | -| LUT3 | 26 | LUT | -| LUT4 | 21 | LUT | -| LUT5 | 13 | LUT | -| LUT2 | 2 | LUT | -+----------+------+---------------------+ - - -8. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -9. Instantiated Netlists ------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vivado.pb deleted file mode 100644 index 1dfb31b4..00000000 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vivado.pb and /dev/null differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst index 5d693691..cdb808b3 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml index 55dd254c..b751b4e8 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf index 4917f361..d50b80fb 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf @@ -6,8 +6,8 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:34:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -15,7 +15,6 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f686f70:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f70686173655f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 @@ -25,12 +24,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3236:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:2331005995 +eof:2018463593 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp index ffae897f..4ed7044e 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b9a2bc45f00e583fa782955fc891e5ceba6f27f0b539960f383a895bca820575 -size 197022 +oid sha256:3dc35a34a7119eefa9d697832940cd52e1981c03235c2e4159dc2da6879f2062 +size 181180 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl index e045b8da..3573a0b4 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl @@ -17,7 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param chipscope.maxJobs 5 set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k410tffg900-2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds index d4709f11..976ff382 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon Jun 12 15:47:26 2023 -# Process ID: 2733301 +# Start of session at: Thu Jun 15 10:53:59 2023 +# Process ID: 658851 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1 # Command line: vivado -log vio_phase_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds @@ -16,34 +16,16 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2733353 +INFO: Helper process launched with PID 658962 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.879 ; gain = 149.688 ; free physical = 17235 ; free virtual = 44627 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.910 ; gain = 149.719 ; free physical = 1052 ; free virtual = 31239 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_phase_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:94] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:87] INFO: [Synth 8-6155] done synthesizing module 'vio_phase_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[5] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] @@ -62,6 +44,25 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bu WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] @@ -122,10 +123,9 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1891.598 ; gain = 211.406 ; free physical = 17255 ; free virtual = 44648 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1891.629 ; gain = 211.438 ; free physical = 1310 ; free virtual = 31095 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,10 +138,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.566 ; gain = 214.375 ; free physical = 17256 ; free virtual = 44649 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.566 ; gain = 214.375 ; free physical = 17256 ; free virtual = 44649 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization @@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2078.223 ; gain = 0.000 ; free physical = 17127 ; free virtual = 44519 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2077.254 ; gain = 0.000 ; free physical = 1178 ; free virtual = 30970 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2086.160 ; gain = 7.938 ; free physical = 17125 ; free virtual = 44517 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2083.191 ; gain = 5.938 ; free physical = 1178 ; free virtual = 30970 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17226 ; free virtual = 44618 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17226 ; free virtual = 44618 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17227 ; free virtual = 44620 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1271 ; free virtual = 31064 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17218 ; free virtual = 44612 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1265 ; free virtual = 31058 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -189,22 +189,21 @@ Start RTL Component Statistics Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 - 2 Input 3 Bit Adders := 1 - 2 Input 1 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 +---Registers : 128 Bit Registers := 1 - 34 Bit Registers := 5 + 33 Bit Registers := 5 16 Bit Registers := 19 - 12 Bit Registers := 9 + 12 Bit Registers := 1 7 Bit Registers := 1 - 5 Bit Registers := 2 - 4 Bit Registers := 2 + 5 Bit Registers := 1 + 4 Bit Registers := 1 3 Bit Registers := 3 - 1 Bit Registers := 28 + 2 Bit Registers := 1 + 1 Bit Registers := 26 +---Muxes : 2 Input 16 Bit Muxes := 2 - 6 Input 12 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 17 + 2 Input 1 Bit Muxes := 10 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -217,17 +216,10 @@ Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : - 34 Bit Registers := 5 + 33 Bit Registers := 5 16 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 2 -Module vio_v3_0_20_probe_width -Detailed RTL Component Info : -+---Adders : - 2 Input 1 Bit Adders := 1 -+---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 Module vio_v3_0_20_probe_out_one Detailed RTL Component Info : +---Registers : @@ -239,33 +231,28 @@ Module vio_v3_0_20_probe_out_one__parameterized0 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 12 Bit Registers := 1 + 1 Bit Registers := 1 +---Muxes : 2 Input 1 Bit Muxes := 1 Module vio_v3_0_20_probe_out_one__parameterized1 Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 1 - 5 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 + 16 Bit Registers := 2 Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 4 Bit Registers := 1 - 1 Bit Registers := 13 + 3 Bit Registers := 1 + 1 Bit Registers := 10 +---Muxes : 2 Input 1 Bit Muxes := 2 -Module vio_v3_0_20_probe_width__parameterized0 +Module vio_v3_0_20_probe_width Detailed RTL Component Info : +---Adders : - 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 - 3 Bit Registers := 1 -+---Muxes : - 6 Input 12 Bit Muxes := 1 + 2 Bit Registers := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -306,114 +293,79 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[0]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[13]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[12]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[13]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[14]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17208 ; free virtual = 44605 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1250 ; free virtual = 31049 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -425,13 +377,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17094 ; free virtual = 44491 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17094 ; free virtual = 44491 +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -443,7 +395,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17087 ; free virtual = 44484 +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30981 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -504,7 +456,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- Report Check Netlist: @@ -517,7 +469,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -529,25 +481,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -560,70 +512,69 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT1 | 3| -|2 |LUT2 | 12| -|3 |LUT3 | 29| -|4 |LUT4 | 99| -|5 |LUT5 | 35| -|6 |LUT6 | 127| -|7 |FDRE | 655| -|8 |FDSE | 4| -+------+-----+------+ ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 3| +|2 |LUT2 | 12| +|3 |LUT3 | 30| +|4 |LUT4 | 82| +|5 |LUT5 | 24| +|6 |LUT6 | 122| +|7 |MUXF7 | 1| +|8 |FDRE | 577| +|9 |FDSE | 2| ++------+------+------+ Report Instance Areas: -+------+----------------------------------------+--------------------------------------------+------+ -| |Instance |Module |Cells | -+------+----------------------------------------+--------------------------------------------+------+ -|1 |top | | 964| -|2 | inst |vio_v3_0_20_vio | 964| -|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 89| -|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 302| -|6 | PROBE_IN_WIDTH_INST |vio_v3_0_20_probe_width | 3| -|7 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 296| -|8 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| -|9 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 10| -|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| -|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 24| -|12 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 24| -|13 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_2 | 24| -|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 24| -|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_4 | 24| -|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_5 | 24| -|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_6 | 24| -|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_7 | 24| -|19 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width__parameterized0 | 10| -+------+----------------------------------------+--------------------------------------------+------+ ++------+---------------------------------------+--------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+--------------------------------------------+------+ +|1 |top | | 853| +|2 | inst |vio_v3_0_20_vio | 853| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 90| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 296| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 198| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| +|9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| +|10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 32| +|12 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_2 | 32| +|13 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_3 | 32| +|14 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_4 | 32| +|15 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 5| ++------+---------------------------------------+--------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 290 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2086.160 ; gain = 214.375 ; free physical = 17143 ; free virtual = 44540 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17157 ; free virtual = 44553 +Synthesis finished with 0 errors, 0 critical warnings and 291 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2083.191 ; gain = 214.406 ; free physical = 1262 ; free virtual = 31037 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1276 ; free virtual = 31050 INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2086.160 ; gain = 0.000 ; free physical = 17069 ; free virtual = 44466 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1192 ; free virtual = 30968 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -118 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +85 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2086.160 ; gain = 687.246 ; free physical = 17163 ; free virtual = 44560 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2086.160 ; gain = 0.000 ; free physical = 17163 ; free virtual = 44560 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2083.191 ; gain = 684.277 ; free physical = 1284 ; free virtual = 31060 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1283 ; free virtual = 31059 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 199e9237e9cad44f -INFO: [Coretcl 2-1174] Renamed 18 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2110.172 ; gain = 0.000 ; free physical = 17166 ; free virtual = 44564 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 0ddc3e874811cad5 +INFO: [Coretcl 2-1174] Renamed 14 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.203 ; gain = 0.000 ; free physical = 1286 ; free virtual = 31064 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon Jun 12 15:47:43 2023... +INFO: [Common 17-206] Exiting Vivado at Thu Jun 15 10:54:16 2023... diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v index 0b827f37..ab5fcf5a 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8997fdff3ed4d2114aaabee05c2bef90cf4fe526231cef8283afd1044c0026a2 -size 451591 +oid sha256:c54161de531f62c9b95a7d5c71ab9df4313489ff5f13778d75d6765db5339e9c +size 425691 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl index b5ac774c..efa6cc2d 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0bc5c8ddccfe953c1e56d33e0a0175daded79f5254373772e1e1e100db6755c9 -size 777511 +oid sha256:06d97b70737529844e27698b1b03e7a08b33b9958b620aa283bd7a6be042800f +size 736925 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v index 6b515e62..2a0bcfb0 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon Jun 12 15:47:42 2023 +// Date : Thu Jun 15 10:54:16 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -14,23 +14,18 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_out0, - probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, - probe_out9, probe_out10) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */; +module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */; input clk; input [31:0]probe_in0; input [0:0]probe_in1; - input [0:0]probe_in2; output [0:0]probe_out0; output [0:0]probe_out1; - output [11:0]probe_out2; - output [11:0]probe_out3; - output [11:0]probe_out4; - output [11:0]probe_out5; - output [11:0]probe_out6; - output [11:0]probe_out7; - output [11:0]probe_out8; - output [11:0]probe_out9; - output [4:0]probe_out10; + output [0:0]probe_out2; + output [0:0]probe_out3; + output [15:0]probe_out4; + output [15:0]probe_out5; + output [15:0]probe_out6; + output [15:0]probe_out7; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl index 71611359..60751ac0 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon Jun 12 15:47:42 2023 +-- Date : Thu Jun 15 10:54:16 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -17,18 +17,14 @@ entity vio_phase_comp is clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 ); - probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ) + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); end vio_phase_comp; @@ -37,7 +33,7 @@ architecture stub of vio_phase_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb index 8995fab6..e9407593 100644 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt index f22b3513..2ee2edd8 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon Jun 12 15:47:42 2023 +| Date : Thu Jun 15 10:54:16 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb | Design : vio_phase_comp @@ -30,13 +30,13 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 284 | 0 | 254200 | 0.11 | -| LUT as Logic | 284 | 0 | 254200 | 0.11 | +| Slice LUTs* | 250 | 0 | 254200 | 0.10 | +| LUT as Logic | 250 | 0 | 254200 | 0.10 | | LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 659 | 0 | 508400 | 0.13 | -| Register as Flip Flop | 659 | 0 | 508400 | 0.13 | +| Slice Registers | 579 | 0 | 508400 | 0.11 | +| Register as Flip Flop | 579 | 0 | 508400 | 0.11 | | Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F7 Muxes | 1 | 0 | 127100 | <0.01 | | F8 Muxes | 0 | 0 | 63550 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -56,8 +56,8 @@ Table of Contents | 0 | Yes | - | - | | 0 | Yes | - | Set | | 0 | Yes | - | Reset | -| 4 | Yes | Set | - | -| 655 | Yes | Reset | - | +| 2 | Yes | Set | - | +| 577 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -151,14 +151,15 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 655 | Flop & Latch | -| LUT6 | 127 | LUT | -| LUT4 | 99 | LUT | -| LUT5 | 35 | LUT | -| LUT3 | 29 | LUT | +| FDRE | 577 | Flop & Latch | +| LUT6 | 122 | LUT | +| LUT4 | 82 | LUT | +| LUT3 | 30 | LUT | +| LUT5 | 24 | LUT | | LUT2 | 12 | LUT | -| FDSE | 4 | Flop & Latch | | LUT1 | 3 | LUT | +| FDSE | 2 | Flop & Latch | +| MUXF7 | 1 | MuxFx | +----------+------+---------------------+ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb index 0caf87b6..4fa78054 100644 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr index 93cb9c37..daf7efb9 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@