archive dj_48m & duifei_online_acq_par

自动频点切换程序已经测试可用,对应程序为duifei_online_acq_par_20230511.xpr和dl814_dj_48m_20230511.xpr
This commit is contained in:
2023-05-11 19:20:44 +08:00
parent c8b75a293f
commit 0f97436c8f
194 changed files with 8097 additions and 3586 deletions
@@ -1133,13 +1133,61 @@
"direction": "OUT",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"rightIndex": 31,
"portIndex": 13,
"nets": [
{
"name": "cnt_valid_to_switch_vio",
"isBus": true,
"subnets": [
{
"name": "cnt_valid_to_switch_vio[31]"
},
{
"name": "cnt_valid_to_switch_vio[30]"
},
{
"name": "cnt_valid_to_switch_vio[29]"
},
{
"name": "cnt_valid_to_switch_vio[28]"
},
{
"name": "cnt_valid_to_switch_vio[27]"
},
{
"name": "cnt_valid_to_switch_vio[26]"
},
{
"name": "cnt_valid_to_switch_vio[25]"
},
{
"name": "cnt_valid_to_switch_vio[24]"
},
{
"name": "cnt_valid_to_switch_vio[23]"
},
{
"name": "cnt_valid_to_switch_vio[22]"
},
{
"name": "cnt_valid_to_switch_vio[21]"
},
{
"name": "cnt_valid_to_switch_vio[20]"
},
{
"name": "cnt_valid_to_switch_vio[19]"
},
{
"name": "cnt_valid_to_switch_vio[18]"
},
{
"name": "cnt_valid_to_switch_vio[17]"
},
{
"name": "cnt_valid_to_switch_vio[16]"
},
{
"name": "cnt_valid_to_switch_vio[15]"
},
@@ -1191,6 +1239,136 @@
]
}
]
},
{
"name": "probe_out14",
"id": 32,
"type": "DATA",
"direction": "OUT",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 14,
"nets": [
{
"name": "auto_test_enable_vio",
"isBus": false
}
]
},
{
"name": "probe_out15",
"id": 33,
"type": "DATA",
"direction": "OUT",
"isVector": true,
"leftIndex": 0,
"rightIndex": 31,
"portIndex": 15,
"nets": [
{
"name": "test_slot_length_vio",
"isBus": true,
"subnets": [
{
"name": "test_slot_length_vio[31]"
},
{
"name": "test_slot_length_vio[30]"
},
{
"name": "test_slot_length_vio[29]"
},
{
"name": "test_slot_length_vio[28]"
},
{
"name": "test_slot_length_vio[27]"
},
{
"name": "test_slot_length_vio[26]"
},
{
"name": "test_slot_length_vio[25]"
},
{
"name": "test_slot_length_vio[24]"
},
{
"name": "test_slot_length_vio[23]"
},
{
"name": "test_slot_length_vio[22]"
},
{
"name": "test_slot_length_vio[21]"
},
{
"name": "test_slot_length_vio[20]"
},
{
"name": "test_slot_length_vio[19]"
},
{
"name": "test_slot_length_vio[18]"
},
{
"name": "test_slot_length_vio[17]"
},
{
"name": "test_slot_length_vio[16]"
},
{
"name": "test_slot_length_vio[15]"
},
{
"name": "test_slot_length_vio[14]"
},
{
"name": "test_slot_length_vio[13]"
},
{
"name": "test_slot_length_vio[12]"
},
{
"name": "test_slot_length_vio[11]"
},
{
"name": "test_slot_length_vio[10]"
},
{
"name": "test_slot_length_vio[9]"
},
{
"name": "test_slot_length_vio[8]"
},
{
"name": "test_slot_length_vio[7]"
},
{
"name": "test_slot_length_vio[6]"
},
{
"name": "test_slot_length_vio[5]"
},
{
"name": "test_slot_length_vio[4]"
},
{
"name": "test_slot_length_vio[3]"
},
{
"name": "test_slot_length_vio[2]"
},
{
"name": "test_slot_length_vio[1]"
},
{
"name": "test_slot_length_vio[0]"
}
]
}
]
}
]
}
@@ -1133,13 +1133,61 @@
"direction": "OUT",
"isVector": true,
"leftIndex": 0,
"rightIndex": 15,
"rightIndex": 31,
"portIndex": 13,
"nets": [
{
"name": "cnt_valid_to_switch_vio",
"isBus": true,
"subnets": [
{
"name": "cnt_valid_to_switch_vio[31]"
},
{
"name": "cnt_valid_to_switch_vio[30]"
},
{
"name": "cnt_valid_to_switch_vio[29]"
},
{
"name": "cnt_valid_to_switch_vio[28]"
},
{
"name": "cnt_valid_to_switch_vio[27]"
},
{
"name": "cnt_valid_to_switch_vio[26]"
},
{
"name": "cnt_valid_to_switch_vio[25]"
},
{
"name": "cnt_valid_to_switch_vio[24]"
},
{
"name": "cnt_valid_to_switch_vio[23]"
},
{
"name": "cnt_valid_to_switch_vio[22]"
},
{
"name": "cnt_valid_to_switch_vio[21]"
},
{
"name": "cnt_valid_to_switch_vio[20]"
},
{
"name": "cnt_valid_to_switch_vio[19]"
},
{
"name": "cnt_valid_to_switch_vio[18]"
},
{
"name": "cnt_valid_to_switch_vio[17]"
},
{
"name": "cnt_valid_to_switch_vio[16]"
},
{
"name": "cnt_valid_to_switch_vio[15]"
},
@@ -1191,6 +1239,136 @@
]
}
]
},
{
"name": "probe_out14",
"id": 32,
"type": "DATA",
"direction": "OUT",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 14,
"nets": [
{
"name": "auto_test_enable_vio",
"isBus": false
}
]
},
{
"name": "probe_out15",
"id": 33,
"type": "DATA",
"direction": "OUT",
"isVector": true,
"leftIndex": 0,
"rightIndex": 31,
"portIndex": 15,
"nets": [
{
"name": "test_slot_length_vio",
"isBus": true,
"subnets": [
{
"name": "test_slot_length_vio[31]"
},
{
"name": "test_slot_length_vio[30]"
},
{
"name": "test_slot_length_vio[29]"
},
{
"name": "test_slot_length_vio[28]"
},
{
"name": "test_slot_length_vio[27]"
},
{
"name": "test_slot_length_vio[26]"
},
{
"name": "test_slot_length_vio[25]"
},
{
"name": "test_slot_length_vio[24]"
},
{
"name": "test_slot_length_vio[23]"
},
{
"name": "test_slot_length_vio[22]"
},
{
"name": "test_slot_length_vio[21]"
},
{
"name": "test_slot_length_vio[20]"
},
{
"name": "test_slot_length_vio[19]"
},
{
"name": "test_slot_length_vio[18]"
},
{
"name": "test_slot_length_vio[17]"
},
{
"name": "test_slot_length_vio[16]"
},
{
"name": "test_slot_length_vio[15]"
},
{
"name": "test_slot_length_vio[14]"
},
{
"name": "test_slot_length_vio[13]"
},
{
"name": "test_slot_length_vio[12]"
},
{
"name": "test_slot_length_vio[11]"
},
{
"name": "test_slot_length_vio[10]"
},
{
"name": "test_slot_length_vio[9]"
},
{
"name": "test_slot_length_vio[8]"
},
{
"name": "test_slot_length_vio[7]"
},
{
"name": "test_slot_length_vio[6]"
},
{
"name": "test_slot_length_vio[5]"
},
{
"name": "test_slot_length_vio[4]"
},
{
"name": "test_slot_length_vio[3]"
},
{
"name": "test_slot_length_vio[2]"
},
{
"name": "test_slot_length_vio[1]"
},
{
"name": "test_slot_length_vio[0]"
}
]
}
]
}
]
}