Archived
archive dj_48m & duifei_online_acq_par
自动频点切换程序已经测试可用,对应程序为duifei_online_acq_par_20230511.xpr和dl814_dj_48m_20230511.xpr
This commit is contained in:
@@ -59,3 +59,7 @@ set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports rx_gain
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set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports tx_gain_6bit ]
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set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports tx_gain_5bit ]
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# Sync Signal
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set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before
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set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before
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-283
@@ -1,283 +0,0 @@
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`pragma protect begin_protected
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`pragma protect version = 1
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`pragma protect encrypt_agent = "XILINX"
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`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
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`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`pragma protect key_block
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XWe4lBDDrw==
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`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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eVhT3XSIJDvufMyiJUc=
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg==
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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R19uHYIhWP+7IpmjTiQ=
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
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`pragma protect data_block
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5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
|
||||
HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
|
||||
pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
|
||||
hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
|
||||
Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
|
||||
dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
|
||||
j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
|
||||
R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
|
||||
0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
|
||||
Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
|
||||
xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
|
||||
eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
|
||||
NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
|
||||
90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
||||
`pragma protect end_protected
|
||||
+6
-2
@@ -62,7 +62,9 @@ probe_out9,
|
||||
probe_out10,
|
||||
probe_out11,
|
||||
probe_out12,
|
||||
probe_out13
|
||||
probe_out13,
|
||||
probe_out14,
|
||||
probe_out15
|
||||
);
|
||||
|
||||
input clk;
|
||||
@@ -81,7 +83,9 @@ output reg [0 : 0] probe_out9 = 'h0 ;
|
||||
output reg [0 : 0] probe_out10 = 'h0 ;
|
||||
output reg [0 : 0] probe_out11 = 'h0 ;
|
||||
output reg [0 : 0] probe_out12 = 'h0 ;
|
||||
output reg [15 : 0] probe_out13 = 'h0000 ;
|
||||
output reg [31 : 0] probe_out13 = 'h00000000 ;
|
||||
output reg [0 : 0] probe_out14 = 'h0 ;
|
||||
output reg [31 : 0] probe_out15 = 'h00000000 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+3
-1
@@ -70,7 +70,9 @@ vio_rf_control your_instance_name (
|
||||
.probe_out10(probe_out10), // output wire [0 : 0] probe_out10
|
||||
.probe_out11(probe_out11), // output wire [0 : 0] probe_out11
|
||||
.probe_out12(probe_out12), // output wire [0 : 0] probe_out12
|
||||
.probe_out13(probe_out13) // output wire [15 : 0] probe_out13
|
||||
.probe_out13(probe_out13), // output wire [31 : 0] probe_out13
|
||||
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
|
||||
.probe_out15(probe_out15) // output wire [31 : 0] probe_out15
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+6
-2
@@ -69,7 +69,9 @@ COMPONENT vio_rf_control
|
||||
probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -95,7 +97,9 @@ your_instance_name : vio_rf_control
|
||||
probe_out10 => probe_out10,
|
||||
probe_out11 => probe_out11,
|
||||
probe_out12 => probe_out12,
|
||||
probe_out13 => probe_out13
|
||||
probe_out13 => probe_out13,
|
||||
probe_out14 => probe_out14,
|
||||
probe_out15 => probe_out15
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+6
-4
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun May 7 19:30:43 2023
|
||||
// Date : Thu May 11 18:52:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
|
||||
@@ -16,8 +16,8 @@
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_rf_control(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12, probe_out13)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]" */;
|
||||
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
|
||||
input clk;
|
||||
input [10:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
@@ -33,5 +33,7 @@ module vio_rf_control(clk, probe_in0, probe_out0, probe_out1,
|
||||
output [0:0]probe_out10;
|
||||
output [0:0]probe_out11;
|
||||
output [0:0]probe_out12;
|
||||
output [15:0]probe_out13;
|
||||
output [31:0]probe_out13;
|
||||
output [0:0]probe_out14;
|
||||
output [31:0]probe_out15;
|
||||
endmodule
|
||||
|
||||
+5
-3
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun May 7 19:30:43 2023
|
||||
-- Date : Thu May 11 18:52:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
|
||||
@@ -29,7 +29,9 @@ entity vio_rf_control is
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end vio_rf_control;
|
||||
@@ -38,7 +40,7 @@ architecture stub of vio_rf_control is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-9
@@ -2,21 +2,13 @@ vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
vlib modelsim_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \
|
||||
"../../../ip/vio_rf_control/sim/vio_rf_control.v" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
|
||||
-3
@@ -1,5 +1,2 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
|
||||
+3
-4
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -95,11 +95,10 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-2
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -102,9 +102,10 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-2
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -93,9 +93,10 @@ setup()
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
-3
@@ -1,5 +1,2 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+4
-12
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
|
||||
vcs_sim_opts="-ucli -licqueue -l simulate.log"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
design_libs=(xil_defaultlib)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
@@ -70,15 +70,6 @@ run()
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \
|
||||
"$ref_dir/../../../ip/vio_rf_control/sim/vio_rf_control.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
@@ -147,9 +138,10 @@ create_lib_mappings()
|
||||
|
||||
touch $file
|
||||
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by export_simulation on Thu May 11 18:51:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 17:52:16 CST 2023
|
||||
# Generated by Vivado on Thu May 11 18:51:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+810
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>5a3cca384525487e</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>vio_rf_control</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN151_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN152_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN153_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN154_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN155_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN156_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN157_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN158_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN159_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN160_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN161_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN162_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN163_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN164_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN165_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN166_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN167_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN168_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN169_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN170_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN171_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN172_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN173_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN174_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN175_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN176_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN177_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN178_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN179_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN180_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN181_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN182_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN183_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN184_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN185_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN186_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN187_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN188_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN189_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN190_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN191_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN192_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN193_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN194_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN195_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN196_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN197_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN198_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN199_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN200_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN201_WIDTH">1</spirit:configurableElementValue>
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</spirit:design>
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BIN
Binary file not shown.
LFS
Executable
BIN
Binary file not shown.
BIN
Binary file not shown.
+39
@@ -0,0 +1,39 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu May 11 18:52:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v
|
||||
// Design : vio_rf_control
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
|
||||
input clk;
|
||||
input [10:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
output [1:0]probe_out1;
|
||||
output [0:0]probe_out2;
|
||||
output [5:0]probe_out3;
|
||||
output [5:0]probe_out4;
|
||||
output [10:0]probe_out5;
|
||||
output [0:0]probe_out6;
|
||||
output [0:0]probe_out7;
|
||||
output [0:0]probe_out8;
|
||||
output [0:0]probe_out9;
|
||||
output [0:0]probe_out10;
|
||||
output [0:0]probe_out11;
|
||||
output [0:0]probe_out12;
|
||||
output [31:0]probe_out13;
|
||||
output [0:0]probe_out14;
|
||||
output [31:0]probe_out15;
|
||||
endmodule
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu May 11 18:52:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl
|
||||
-- Design : vio_rf_control
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+5
-5
@@ -1,9 +1,9 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3136:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3339:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3433:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:33:00:00
|
||||
@@ -25,8 +25,8 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:36:00:00
|
||||
eof:283634649
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:37:00:00
|
||||
eof:721564357
|
||||
|
||||
+3
-3
@@ -4,6 +4,6 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:37:00:00
|
||||
eof:905549317
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:39:00:00
|
||||
eof:1561787943
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:7
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:8
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:726f6d5f667265715f776f7264:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f72665f636f6e74726f6c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333473:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323135302e3135364d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3734392e3233384d42:00:00
|
||||
eof:1256184425
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131322e3639354d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730372e3834304d42:00:00
|
||||
eof:3078012162
|
||||
|
||||
+9
-9
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Mon May 8 19:06:15 2023">
|
||||
<application name="pa" timeStamp="Thu May 11 18:57:44 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="b252a1e4ed8d4787b074893bfbb0dee3" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -22,15 +22,15 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="EditDelete" value="2" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="1" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="7" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="7" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="9" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="16" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="17" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="39" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="43" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="3" type="GuiHandlerData"/>
|
||||
@@ -52,15 +52,15 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="5" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="6" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="2" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="7" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="115" type="GuiMode"/>
|
||||
<property name="GuiMode" value="123" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="82" type="TclMode"/>
|
||||
<property name="TclMode" value="87" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_rf_control_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+3
-6
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rom_freq_word_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1683543324">
|
||||
<File Type="VDS-TIMING-PB" Name="rom_freq_word_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="rom_freq_word_timing_summary_synth.rpt"/>
|
||||
<File Type="PA-TCL" Name="rom_freq_word.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="rom_freq_word_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="rom_freq_word.vds"/>
|
||||
<File Type="RDS-DCP" Name="rom_freq_word.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rom_freq_word_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="rom_freq_word_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="rom_freq_word_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="rom_freq_word.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="rom_freq_word_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="rom_freq_word.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_freq_word">
|
||||
<File Path="$PPRDIR/../rom_freq_word.xcix">
|
||||
<FileInfo>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1683539743">
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="770578" HostCore="20" HostMemory="65588992">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rf_control_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1683802313">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_rf_control_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_rf_control_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_rf_control.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_rf_control_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="vio_rf_control.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_rf_control.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="vio_rf_control_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rf_control_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rf_control_utilization_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rf_control">
|
||||
<File Path="$PPRDIR/../vio_rf_control/vio_rf_control.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rf_control.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_rf_control"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rf_control">
|
||||
<File Path="$PPRDIR/../vio_rf_control/vio_rf_control.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rf_control.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_rf_control"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl
|
||||
+37
@@ -0,0 +1,37 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f34386d5f746f5f3132327038386d:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6c70665f3132356b:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f667265715f776f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c7369675f636c6b5f67656e:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3132:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00
|
||||
eof:3012764614
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl
|
||||
BIN
Binary file not shown.
+155
@@ -0,0 +1,155 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1 -new_name vio_rf_control -ip [get_ips vio_rf_control]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix vio_rf_control_ vio_rf_control.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v
|
||||
lappend ipCachedFiles vio_rf_control_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl
|
||||
lappend ipCachedFiles vio_rf_control_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.v
|
||||
lappend ipCachedFiles vio_rf_control_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.vhdl
|
||||
lappend ipCachedFiles vio_rf_control_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp vio_rf_control.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rf_control]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all vio_rf_control_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef vio_rf_control.dcp
|
||||
create_report "vio_rf_control_synth_1_synth_report_utilization_0" "report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci]
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+664
@@ -0,0 +1,664 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu May 11 18:51:54 2023
|
||||
# Process ID: 770617
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1
|
||||
# Command line: vivado -log vio_rf_control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds
|
||||
# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source vio_rf_control.tcl -notrace
|
||||
Command: synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100'
|
||||
INFO: [Device 21-403] Loading part xc7z100ffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 773070
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.477 ; gain = 153.688 ; free physical = 1081 ; free virtual = 43261
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_rf_control' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/synth/vio_rf_control.v:59]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rf_control does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/synth/vio_rf_control.v:102]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_rf_control' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/synth/vio_rf_control.v:59]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.164 ; gain = 215.375 ; free physical = 1103 ; free virtual = 43284
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.133 ; gain = 218.344 ; free physical = 1102 ; free virtual = 43284
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.133 ; gain = 218.344 ; free physical = 1102 ; free virtual = 43284
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc]
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc]
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xdc]
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.758 ; gain = 0.000 ; free physical = 999 ; free virtual = 43181
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2112.695 ; gain = 5.938 ; free physical = 999 ; free virtual = 43181
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 1100 ; free virtual = 43283
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z100ffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 1100 ; free virtual = 43283
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 1095 ; free virtual = 43278
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 1052 ; free virtual = 43243
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 3 Bit Adders := 1
|
||||
2 Input 2 Bit Adders := 2
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
32 Bit Registers := 2
|
||||
16 Bit Registers := 26
|
||||
13 Bit Registers := 1
|
||||
11 Bit Registers := 5
|
||||
7 Bit Registers := 1
|
||||
6 Bit Registers := 2
|
||||
5 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
3 Bit Registers := 3
|
||||
2 Bit Registers := 3
|
||||
1 Bit Registers := 40
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 4
|
||||
8 Input 13 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 21
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module vio_v3_0_20_probe_in_one
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
11 Bit Registers := 4
|
||||
1 Bit Registers := 2
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized0
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
2 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized1
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized2
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized3
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
11 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized4
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 2 Bit Adders := 1
|
||||
+---Registers :
|
||||
32 Bit Registers := 1
|
||||
16 Bit Registers := 3
|
||||
2 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_all
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 18
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 2
|
||||
Module vio_v3_0_20_probe_width
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 3 Bit Adders := 1
|
||||
+---Registers :
|
||||
13 Bit Registers := 1
|
||||
3 Bit Registers := 1
|
||||
+---Muxes :
|
||||
8 Input 13 Bit Muxes := 1
|
||||
Module xsdbs_v1_0_2_xsdbs
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
16 Bit Registers := 2
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 2
|
||||
7 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
3 Bit Registers := 2
|
||||
1 Bit Registers := 9
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 3
|
||||
Module vio_v3_0_20_vio
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 2020 (col length:140)
|
||||
BRAMs: 1510 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 1060 ; free virtual = 43254
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 891 ; free virtual = 43097
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 1|
|
||||
|2 |LUT2 | 15|
|
||||
|3 |LUT3 | 80|
|
||||
|4 |LUT4 | 9|
|
||||
|5 |LUT5 | 28|
|
||||
|6 |LUT6 | 99|
|
||||
|7 |MUXF7 | 7|
|
||||
|8 |MUXF8 | 1|
|
||||
|9 |FDRE | 530|
|
||||
|10 |FDSE | 20|
|
||||
+------+------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
|1 |top | | 790|
|
||||
|2 | inst |vio_v3_0_20_vio | 790|
|
||||
|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248|
|
||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 86|
|
||||
|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 58|
|
||||
|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 366|
|
||||
|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
||||
|8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3|
|
||||
|9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3|
|
||||
|10 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3|
|
||||
|11 | \G_PROBE_OUT[13].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 101|
|
||||
|12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3|
|
||||
|13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_4 | 106|
|
||||
|14 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 6|
|
||||
|15 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_5 | 3|
|
||||
|16 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 12|
|
||||
|17 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 12|
|
||||
|18 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 22|
|
||||
|19 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3|
|
||||
|20 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3|
|
||||
|21 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_8 | 3|
|
||||
|22 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_9 | 3|
|
||||
|23 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 16|
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 892 ; free virtual = 43098
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 292 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2112.695 ; gain = 218.344 ; free physical = 950 ; free virtual = 43156
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2112.695 ; gain = 405.906 ; free physical = 964 ; free virtual = 43170
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.695 ; gain = 0.000 ; free physical = 882 ; free virtual = 43088
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
130 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2112.695 ; gain = 713.777 ; free physical = 974 ; free virtual = 43181
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2112.695 ; gain = 0.000 ; free physical = 974 ; free virtual = 43181
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rf_control, cache-ID = 5a3cca384525487e
|
||||
INFO: [Coretcl 2-1174] Renamed 22 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2136.707 ; gain = 0.000 ; free physical = 951 ; free virtual = 43160
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu May 11 18:52:12 2023...
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+39
@@ -0,0 +1,39 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu May 11 18:52:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
|
||||
// Design : vio_rf_control
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_rf_control(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
|
||||
input clk;
|
||||
input [10:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
output [1:0]probe_out1;
|
||||
output [0:0]probe_out2;
|
||||
output [5:0]probe_out3;
|
||||
output [5:0]probe_out4;
|
||||
output [10:0]probe_out5;
|
||||
output [0:0]probe_out6;
|
||||
output [0:0]probe_out7;
|
||||
output [0:0]probe_out8;
|
||||
output [0:0]probe_out9;
|
||||
output [0:0]probe_out10;
|
||||
output [0:0]probe_out11;
|
||||
output [0:0]probe_out12;
|
||||
output [31:0]probe_out13;
|
||||
output [0:0]probe_out14;
|
||||
output [31:0]probe_out15;
|
||||
endmodule
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu May 11 18:52:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
|
||||
-- Design : vio_rf_control
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_rf_control is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end vio_rf_control;
|
||||
|
||||
architecture stub of vio_rf_control is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+183
@@ -0,0 +1,183 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Thu May 11 18:52:11 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb
|
||||
| Design : vio_rf_control
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 189 | 0 | 277400 | 0.07 |
|
||||
| LUT as Logic | 189 | 0 | 277400 | 0.07 |
|
||||
| LUT as Memory | 0 | 0 | 108200 | 0.00 |
|
||||
| Slice Registers | 550 | 0 | 554800 | 0.10 |
|
||||
| Register as Flip Flop | 550 | 0 | 554800 | 0.10 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 7 | 0 | 138700 | <0.01 |
|
||||
| F8 Muxes | 1 | 0 | 69350 | <0.01 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 20 | Yes | Set | - |
|
||||
| 530 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1510 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 2020 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 530 | Flop & Latch |
|
||||
| LUT6 | 99 | LUT |
|
||||
| LUT3 | 80 | LUT |
|
||||
| LUT5 | 28 | LUT |
|
||||
| FDSE | 20 | Flop & Latch |
|
||||
| LUT2 | 15 | LUT |
|
||||
| LUT4 | 9 | LUT |
|
||||
| MUXF7 | 7 | MuxFx |
|
||||
| MUXF8 | 1 | MuxFx |
|
||||
| LUT1 | 1 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
BIN
Binary file not shown.
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="12"/>
|
||||
<Option Name="WTModelSimExportSim" Val="12"/>
|
||||
<Option Name="WTQuestaExportSim" Val="12"/>
|
||||
<Option Name="WTIesExportSim" Val="12"/>
|
||||
<Option Name="WTVcsExportSim" Val="12"/>
|
||||
<Option Name="WTRivieraExportSim" Val="12"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="12"/>
|
||||
<Option Name="WTXSimExportSim" Val="13"/>
|
||||
<Option Name="WTModelSimExportSim" Val="13"/>
|
||||
<Option Name="WTQuestaExportSim" Val="13"/>
|
||||
<Option Name="WTIesExportSim" Val="13"/>
|
||||
<Option Name="WTVcsExportSim" Val="13"/>
|
||||
<Option Name="WTRivieraExportSim" Val="13"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="13"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -114,20 +114,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rf_control.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rf_control/vio_rf_control.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
@@ -195,6 +181,26 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="vio_rf_control" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rf_control">
|
||||
<File Path="$PPRDIR/../vio_rf_control.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../vio_rf_control/vio_rf_control.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_rf_control"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -247,6 +253,17 @@
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="vio_rf_control_synth_1" Type="Ft3:Synth" SrcSet="vio_rf_control" Part="xc7z100ffg900-2" ConstrsSet="vio_rf_control" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_rf_control_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
@@ -295,6 +312,24 @@
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="vio_rf_control_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="vio_rf_control" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_rf_control_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
|
||||
Binary file not shown.
@@ -3,7 +3,7 @@
|
||||
#
|
||||
# project.tcl: Tcl script for re-creating project 'project'
|
||||
#
|
||||
# Generated by Vivado on Mon May 08 19:06:00 CST 2023
|
||||
# Generated by Vivado on Thu May 11 19:05:20 CST 2023
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
@@ -164,7 +164,6 @@ set_property -name "webtalk.modelsim_export_sim" -value "36" -objects $obj
|
||||
set_property -name "webtalk.questa_export_sim" -value "36" -objects $obj
|
||||
set_property -name "webtalk.riviera_export_sim" -value "36" -objects $obj
|
||||
set_property -name "webtalk.vcs_export_sim" -value "36" -objects $obj
|
||||
set_property -name "webtalk.xcelium_export_sim" -value "3" -objects $obj
|
||||
set_property -name "webtalk.xsim_export_sim" -value "36" -objects $obj
|
||||
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
|
||||
|
||||
|
||||
@@ -1133,13 +1133,61 @@
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 15,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 13,
|
||||
"nets": [
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[31]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[30]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[29]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[28]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[27]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[26]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[25]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[24]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[23]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[22]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[21]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[20]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[19]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[18]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[17]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[16]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[15]"
|
||||
},
|
||||
@@ -1191,6 +1239,136 @@
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out14",
|
||||
"id": 32,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": false,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 0,
|
||||
"portIndex": 14,
|
||||
"nets": [
|
||||
{
|
||||
"name": "auto_test_enable_vio",
|
||||
"isBus": false
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out15",
|
||||
"id": 33,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 15,
|
||||
"nets": [
|
||||
{
|
||||
"name": "test_slot_length_vio",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "test_slot_length_vio[31]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[30]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[29]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[28]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[27]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[26]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[25]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[24]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[23]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[22]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[21]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[20]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[19]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[18]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[17]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[16]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[15]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[14]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[13]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[12]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[11]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[10]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[9]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[8]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[7]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[6]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[5]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[4]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[3]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[2]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[1]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1133,13 +1133,61 @@
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 15,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 13,
|
||||
"nets": [
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[31]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[30]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[29]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[28]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[27]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[26]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[25]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[24]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[23]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[22]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[21]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[20]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[19]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[18]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[17]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[16]"
|
||||
},
|
||||
{
|
||||
"name": "cnt_valid_to_switch_vio[15]"
|
||||
},
|
||||
@@ -1191,6 +1239,136 @@
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out14",
|
||||
"id": 32,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": false,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 0,
|
||||
"portIndex": 14,
|
||||
"nets": [
|
||||
{
|
||||
"name": "auto_test_enable_vio",
|
||||
"isBus": false
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"name": "probe_out15",
|
||||
"id": 33,
|
||||
"type": "DATA",
|
||||
"direction": "OUT",
|
||||
"isVector": true,
|
||||
"leftIndex": 0,
|
||||
"rightIndex": 31,
|
||||
"portIndex": 15,
|
||||
"nets": [
|
||||
{
|
||||
"name": "test_slot_length_vio",
|
||||
"isBus": true,
|
||||
"subnets": [
|
||||
{
|
||||
"name": "test_slot_length_vio[31]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[30]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[29]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[28]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[27]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[26]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[25]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[24]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[23]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[22]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[21]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[20]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[19]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[18]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[17]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[16]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[15]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[14]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[13]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[12]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[11]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[10]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[9]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[8]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[7]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[6]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[5]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[4]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[3]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[2]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[1]"
|
||||
},
|
||||
{
|
||||
"name": "test_slot_length_vio[0]"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -1,44 +1,47 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2023/05/06 15:37:29
|
||||
// Design Name:
|
||||
// Design Name:
|
||||
// Module Name: rf_auto_switch_freq
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module rf_auto_switch_freq(
|
||||
input clk ,
|
||||
input rst ,
|
||||
input clk ,
|
||||
input rst ,
|
||||
// vio control
|
||||
input start , // rise-edge active, if start, change freq word to the first
|
||||
input auto_test_enable , // rise-edge active
|
||||
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
|
||||
input switch_next_freq , // rise-edge active
|
||||
input switch_last_freq , // rise-edge active
|
||||
input [15:0] cnt_valid_to_switch , // clock number from valid to switch
|
||||
input [31:0] cnt_valid_to_switch , // clock number from valid to switch
|
||||
input [31:0] test_slot_length ,
|
||||
// input
|
||||
input [10:0] freq_hop_words_vio ,
|
||||
input hop_words_valid_vio ,
|
||||
input freq_hop_switch_vio ,
|
||||
// output
|
||||
input [10:0] freq_hop_words_vio ,
|
||||
input hop_words_valid_vio ,
|
||||
input freq_hop_switch_vio ,
|
||||
// output
|
||||
output reg [10:0] freq_hop_words_auto = 11'd0 ,
|
||||
output reg hop_words_valid_auto = 1'd0 ,
|
||||
output reg freq_hop_switch_auto = 1'd0
|
||||
output reg freq_hop_switch_auto = 1'd0 ,
|
||||
output reg sync_signal = 1'b0 // sync signal from DJ to JD
|
||||
);
|
||||
|
||||
|
||||
//************************* rise-edge detect ***********************************
|
||||
reg start_d1 = 1'b0;
|
||||
reg start_d2 = 1'b0;
|
||||
@@ -49,6 +52,9 @@ reg [9:0] switch_next_freq_pulse = 10'd0;
|
||||
reg switch_last_freq_d1 = 1'b0;
|
||||
reg switch_last_freq_d2 = 1'b0;
|
||||
reg [9:0] switch_last_freq_pulse = 10'd0;
|
||||
reg auto_test_enable_d1 = 1'b0;
|
||||
reg auto_test_enable_d2 = 1'b0;
|
||||
reg auto_test_enable_pulse = 1'b0;
|
||||
always @ (posedge clk)
|
||||
if(rst) begin
|
||||
start_d1 <= 1'b0;
|
||||
@@ -60,6 +66,9 @@ always @ (posedge clk)
|
||||
switch_last_freq_d1 <= 1'b0;
|
||||
switch_last_freq_d2 <= 1'b0;
|
||||
switch_last_freq_pulse <= 10'd0;
|
||||
auto_test_enable_d1 <= 1'b0;
|
||||
auto_test_enable_d2 <= 1'b0;
|
||||
auto_test_enable_pulse <= 1'b0;
|
||||
end else begin
|
||||
start_d1 <= start;
|
||||
start_d2 <= start_d1;
|
||||
@@ -72,13 +81,35 @@ always @ (posedge clk)
|
||||
switch_last_freq_d2 <= switch_last_freq_d1;
|
||||
switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2;
|
||||
switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0];
|
||||
auto_test_enable_d1 <= auto_test_enable;
|
||||
auto_test_enable_d2 <= auto_test_enable_d1;
|
||||
auto_test_enable_pulse <= auto_test_enable_d1 & ~auto_test_enable_d2;
|
||||
end
|
||||
|
||||
//************************ auto test logic *************************************
|
||||
reg auto_test_enable_reg = 1'b0;
|
||||
reg [31:0] auto_test_cnt = 32'd0;
|
||||
reg [7:0] freq_word_cnt = 8'd0; // range 0 -> 80
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
auto_test_enable_reg <= 1'b0;
|
||||
else if(auto_test_enable_pulse && ~auto_test_enable_reg)
|
||||
auto_test_enable_reg <= 1'b1;
|
||||
else if(auto_test_cnt == test_slot_length && freq_word_cnt == 8'd80)
|
||||
auto_test_enable_reg <= 1'b0;
|
||||
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
auto_test_cnt <= 32'd0;
|
||||
else if(auto_test_cnt == test_slot_length)
|
||||
auto_test_cnt <= 32'd0;
|
||||
else if(auto_test_enable_reg)
|
||||
auto_test_cnt <= auto_test_cnt + 1'b1;
|
||||
|
||||
//******************** local freq word control *********************************
|
||||
reg [10:0] local_freq_word = 11'd0;
|
||||
reg local_freq_word_valid = 1'b0;
|
||||
reg local_freq_word_switch = 1'b0;
|
||||
reg [7:0] freq_word_cnt = 8'd0; // range 0 -> 80
|
||||
wire [10:0] rom_freq_word_dout;
|
||||
// 2 clock latency
|
||||
rom_freq_word rom_freq_word_inst(
|
||||
@@ -92,8 +123,12 @@ always @ (posedge clk)
|
||||
freq_word_cnt <= 8'd0;
|
||||
else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0])
|
||||
freq_word_cnt <= 8'd0;
|
||||
else if(freq_word_cnt == 8'd80 && auto_test_cnt == test_slot_length)
|
||||
freq_word_cnt <= 8'd0;
|
||||
else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0])
|
||||
freq_word_cnt <= 8'd80;
|
||||
else if(auto_test_cnt == test_slot_length)
|
||||
freq_word_cnt <= freq_word_cnt + 1'b1;
|
||||
else if(switch_next_freq_pulse[0])
|
||||
freq_word_cnt <= freq_word_cnt + 1'b1;
|
||||
else if(switch_last_freq_pulse[0])
|
||||
@@ -104,20 +139,20 @@ always @ (posedge clk)
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
local_freq_word_valid <= 1'b0;
|
||||
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4])
|
||||
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | auto_test_cnt == 32'd4)
|
||||
local_freq_word_valid <= 1'b1;
|
||||
else
|
||||
else if(auto_test_cnt == 32'd104)
|
||||
local_freq_word_valid <= 1'b0;
|
||||
|
||||
reg [15:0] freq_word_valid_cnt = 16'd0;
|
||||
reg [31:0] freq_word_valid_cnt = 32'd0;
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
freq_word_valid_cnt <= 16'd0;
|
||||
freq_word_valid_cnt <= 32'd0;
|
||||
else if(freq_word_valid_cnt == cnt_valid_to_switch)
|
||||
freq_word_valid_cnt <= 16'd0;
|
||||
freq_word_valid_cnt <= 32'd0;
|
||||
else if(local_freq_word_valid)
|
||||
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
|
||||
else if(freq_word_valid_cnt != 16'd0)
|
||||
else if(freq_word_valid_cnt != 32'd0)
|
||||
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
|
||||
else
|
||||
freq_word_valid_cnt <= freq_word_valid_cnt;
|
||||
@@ -125,11 +160,13 @@ always @ (posedge clk)
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
local_freq_word_switch <= 1'b0;
|
||||
else if(freq_word_valid_cnt == cnt_valid_to_switch)
|
||||
else if(freq_word_valid_cnt == cnt_valid_to_switch - 32'd100)
|
||||
local_freq_word_switch <= 1'b1;
|
||||
else
|
||||
else if(freq_word_valid_cnt == cnt_valid_to_switch)
|
||||
local_freq_word_switch <= 1'b0;
|
||||
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
local_freq_word <= 11'd0;
|
||||
@@ -154,7 +191,7 @@ always @ (posedge clk)
|
||||
hop_words_valid_auto <= local_freq_word_valid;
|
||||
else
|
||||
hop_words_valid_auto <= hop_words_valid_vio;
|
||||
|
||||
|
||||
// freq_hop_switch_auto
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
@@ -163,5 +200,12 @@ always @ (posedge clk)
|
||||
freq_hop_switch_auto <= local_freq_word_switch;
|
||||
else
|
||||
freq_hop_switch_auto <= freq_hop_switch_vio;
|
||||
|
||||
|
||||
// sync_signal
|
||||
always @ (posedge clk)
|
||||
if(rst | start_pulse)
|
||||
sync_signal <= 1'b0;
|
||||
else if(~freq_hop_switch_auto & local_freq_word_switch)
|
||||
sync_signal <= ~sync_signal;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -109,7 +109,12 @@ module system_top
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb
|
||||
inout fixed_io_ps_srstb ,
|
||||
// *************************************************************************
|
||||
// ************************* Sync Signal ***********************************
|
||||
// *************************************************************************
|
||||
output sync_signal_out ,
|
||||
output reg sync_gnd = 1'b0
|
||||
);
|
||||
|
||||
|
||||
@@ -278,11 +283,13 @@ assign rx_gain_4bit = rx_gain[4];
|
||||
assign rx_gain_3bit = rx_gain[3];
|
||||
|
||||
// rf auto switch frequency function
|
||||
wire auto_test_enable_vio;
|
||||
wire rf_auto_start_vio ;
|
||||
wire rf_ctrl_mode_vio ;
|
||||
wire switch_next_freq_vio;
|
||||
wire switch_last_freq_vio;
|
||||
wire [15:0] cnt_valid_to_switch_vio;
|
||||
wire [31:0] cnt_valid_to_switch_vio;
|
||||
wire [31:0] test_slot_length_vio;
|
||||
|
||||
wire [10:0] freq_hop_words_auto ;
|
||||
wire hop_words_valid_auto;
|
||||
@@ -293,10 +300,12 @@ rf_auto_switch_freq u_rf_auto_switch_freq(
|
||||
.rst (sys_rst ),
|
||||
// vio control
|
||||
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
|
||||
.auto_test_enable (auto_test_enable_vio ), // rise-edge active
|
||||
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
|
||||
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
|
||||
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
|
||||
.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
|
||||
.cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch
|
||||
.test_slot_length (test_slot_length_vio[31:0] ),
|
||||
// input
|
||||
.freq_hop_words_vio (freq_hop_words_vio[10:0] ),
|
||||
.hop_words_valid_vio (hop_words_valid_vio ),
|
||||
@@ -304,46 +313,38 @@ rf_auto_switch_freq u_rf_auto_switch_freq(
|
||||
// output
|
||||
.freq_hop_words_auto (freq_hop_words_auto[10:0] ),
|
||||
.hop_words_valid_auto (hop_words_valid_auto ),
|
||||
.freq_hop_switch_auto (freq_hop_switch_auto )
|
||||
.freq_hop_switch_auto (freq_hop_switch_auto ),
|
||||
.sync_signal (sync_signal_out )
|
||||
);
|
||||
|
||||
rf_control u_rf_control
|
||||
(
|
||||
rf_control u_rf_control(
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
|
||||
//input
|
||||
.gain_on_vio (gain_on_vio ),
|
||||
.rf_txrx_vio (rf_txrx_vio[1:0] ),
|
||||
.rf_txrx_net (2'd0 ),
|
||||
|
||||
.tx_gain_manual (tx_gain_manual[5:0] ),
|
||||
.rx_gain_manual (rx_gain_manual[5:0] ),
|
||||
|
||||
//0:net->control 1:vio->control
|
||||
.rf_vio_set (rf_vio_set ),
|
||||
|
||||
//vio hop control
|
||||
.freq_hop_words_vio (freq_hop_words_auto[10:0] ),
|
||||
.hop_words_valid_vio (hop_words_valid_auto ),
|
||||
.freq_hop_switch_vio (freq_hop_switch_auto ),
|
||||
|
||||
//tx hop control
|
||||
.tx_freq_hop_words (11'b0 ),
|
||||
.tx_hop_words_valid (1'b0 ),
|
||||
.tx_freq_hop_switch (1'b0 ),
|
||||
|
||||
//rx hop control
|
||||
.rx_freq_hop_words (11'b0 ),
|
||||
.rx_hop_words_valid (1'b0 ),
|
||||
.rx_freq_hop_switch (1'b0 ),
|
||||
|
||||
//output
|
||||
.tx_gain (tx_gain[11:0] ),
|
||||
.tx_gain_on (tx_gain_on ),
|
||||
.rx_gain (rx_gain[9:0] ),
|
||||
.rx_gain_on (rx_gain_on ),
|
||||
|
||||
.freq_hop_words (freq_hop_words[10:0] ),
|
||||
.hop_words_valid (hop_words_valid ),
|
||||
.freq_hop_switch (freq_hop_switch ),
|
||||
@@ -351,6 +352,7 @@ rf_control u_rf_control
|
||||
);
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////// Tx Baseband Signals //////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@@ -476,7 +478,9 @@ vio_rf_control u_vio_rf_control
|
||||
.probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10
|
||||
.probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11
|
||||
.probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12
|
||||
.probe_out13 (cnt_valid_to_switch_vio[15:0] ), // output wire [15: 0] probe_out13
|
||||
.probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13
|
||||
.probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14
|
||||
.probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15
|
||||
.probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0
|
||||
);
|
||||
|
||||
|
||||
@@ -16,6 +16,8 @@ interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 8192;
|
||||
fs = 48e6;
|
||||
freqRange = -15000:20:-5000;
|
||||
|
||||
dataFile = [ ...
|
||||
"iladata_25.0G_1-A-1-1.csv", ...
|
||||
"iladata_25.0G_1-A-1-2.csv", ...
|
||||
@@ -150,34 +152,6 @@ dataFile = [ ...
|
||||
"iladata_600_1800_27.0G_1-1.csv", ...
|
||||
"iladata_600_1800_27.0G_1-2.csv", ...
|
||||
"iladata_600_1800_27.0G_1-3.csv", ...
|
||||
"iladata_cal_000_0000_00_00_26.0G_1.csv", ...
|
||||
"iladata_cal_000_0000_00_00_26.0G_2.csv", ...
|
||||
"iladata_cal_000_0000_00_00_26.0G_3.csv", ...
|
||||
"iladata_cal_000_0000_00_00_27.0G_1.csv", ...
|
||||
"iladata_cal_000_0000_00_00_27.0G_2.csv", ...
|
||||
"iladata_cal_000_0000_00_00_27.0G_3.csv", ...
|
||||
"iladata_cal_000_0000_20_20_26.0G_1.csv", ...
|
||||
"iladata_cal_000_0000_20_20_26.0G_2.csv", ...
|
||||
"iladata_cal_000_0000_20_20_26.0G_3.csv", ...
|
||||
"iladata_cal_000_0000_20_20_27.0G_1.csv", ...
|
||||
"iladata_cal_000_0000_20_20_27.0G_2.csv", ...
|
||||
"iladata_cal_000_0000_20_20_27.0G_3.csv", ...
|
||||
"iladata_cal_25.0G.csv", ...
|
||||
"iladata_cal_25.0G_result.csv", ...
|
||||
"iladata_cal_26.0G.csv", ...
|
||||
"iladata_cal_27.0G.csv", ...
|
||||
"iladata_cal_414_3109_00_00_27.0G_1.csv", ...
|
||||
"iladata_cal_414_3109_00_00_27.0G_2.csv", ...
|
||||
"iladata_cal_414_3109_00_00_27.0G_3.csv", ...
|
||||
"iladata_cal_414_3109_30_30_27.0G_1.csv", ...
|
||||
"iladata_cal_414_3109_30_30_27.0G_2.csv", ...
|
||||
"iladata_cal_414_3109_30_30_27.0G_3.csv", ...
|
||||
"iladata_cal_600_3150_30_30_27.0G_1.csv", ...
|
||||
"iladata_cal_600_3150_30_30_27.0G_2.csv", ...
|
||||
"iladata_cal_600_3150_30_30_27.0G_3.csv", ...
|
||||
"iladata_cal_600_3150_38_51_27.0G_1.csv", ...
|
||||
"iladata_cal_600_3150_38_51_27.0G_2.csv", ...
|
||||
"iladata_cal_600_3150_38_51_27.0G_3.csv", ...
|
||||
];
|
||||
|
||||
dataFileNum = length(dataFile);
|
||||
@@ -194,7 +168,6 @@ symNum = dataLen/chipLen/interp; % total symbol number
|
||||
%% data analysis
|
||||
|
||||
% search for frequency shift
|
||||
freqRange = -20000:50:0;
|
||||
freqDmfPeak = zeros(dataFileNum,length(freqRange));
|
||||
freqTarget = zeros(dataFileNum,channelNum);
|
||||
|
||||
@@ -239,7 +212,7 @@ for data_num = 1:dataFileNum
|
||||
% convolve multiplied data with pn sequence, without zero-padded results
|
||||
data_dmf = conv(data_cxr, kron(flip(PRBS7_polar),ones(interp,1)),'valid');
|
||||
% peak search
|
||||
freqDmfPeak(data_num,freq_num) = max(data_dmf(1:end-1));
|
||||
freqDmfPeak(data_num,freq_num) = max(abs(data_dmf(1:end-1)));
|
||||
end
|
||||
freqTarget(data_num,ch_num) = freqRange(freqDmfPeak(data_num,:) == ...
|
||||
max(freqDmfPeak(data_num,:)));
|
||||
@@ -280,6 +253,8 @@ for data_num = 1:dataFileNum
|
||||
end
|
||||
|
||||
freqTargetRelative = freqTarget - freqTarget(:,1);
|
||||
freqTargetMax = max(freqTarget,[],'all');
|
||||
freqTargetMin = min(freqTarget,[],'all');
|
||||
maxDesiredPointIndexDiff = max(abs(desiredPntIndex-(desiredPntIndex(:,:,1))),[],"all");
|
||||
|
||||
ampEstSymMaxList = strings(dataFileNum+1,channelNum+1);
|
||||
|
||||
@@ -1,192 +0,0 @@
|
||||
%% File Header/文件说明
|
||||
%
|
||||
% Beamforming with phased array derives signal characteristics from phase
|
||||
% differences between sensors. Therefore the amplitude-phase consistence is
|
||||
% vital to phased systems.
|
||||
%
|
||||
% The script analyzes the amp-phase relations of ILA captured data, the format
|
||||
% of which is square-shaped pseudorandorm bit sequence. Each channel is
|
||||
% processed seperately with different frequency shifts and different optimum
|
||||
% sampling points. The estimation of amplitude and phase are based on
|
||||
% acculumated correlation peaks.
|
||||
%
|
||||
clc; clear;
|
||||
%% initial parameters/初始参数
|
||||
interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 8192;
|
||||
fs = 48e6;
|
||||
dataFile = [ ...
|
||||
% "iladata_rx_data_26G_20230509_1445.csv", ...
|
||||
% "iladata_rx_data_26G_20230509_1715.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1030.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1100.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1115.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1415_A-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1415_A-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1415_A-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1455_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1455_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1455_B-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1500_A-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1500_A-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1500_A-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1530_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1530_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1530_B-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1600_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1600_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1630_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1630_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1630_B-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1725_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1725_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1725_B-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1730_A-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1730_A-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1730_A-3.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1740_B-1.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1740_B-2.csv", ...
|
||||
"iladata_rx_data_26G_20230510_1740_B-3.csv", ...
|
||||
];
|
||||
|
||||
dataFileNum = length(dataFile);
|
||||
|
||||
% standard pn sequence
|
||||
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||
PRBS7 = pnSequence();
|
||||
PRBS7_polar = 1-2*[PRBS7;0];
|
||||
|
||||
chipLen = length(PRBS7_polar); % pn chip length
|
||||
symNum = dataLen/chipLen/interp; % total symbol number
|
||||
|
||||
%% data analysis
|
||||
|
||||
% search for frequency shift
|
||||
freqRange = 22000:10:28000;
|
||||
freqDmfPeak = zeros(dataFileNum,length(freqRange));
|
||||
freqTarget = zeros(dataFileNum,channelNum);
|
||||
|
||||
% phase amplitude analysis
|
||||
desiredPnt = zeros(dataFileNum,symNum-1,channelNum);
|
||||
desiredPntIndex = zeros(dataFileNum,symNum-1,channelNum);
|
||||
|
||||
ampEstSymRaw = zeros(dataFileNum,symNum-1,channelNum);
|
||||
ampEstSymMin = zeros(dataFileNum,channelNum);
|
||||
ampEstSymMax = zeros(dataFileNum,channelNum);
|
||||
ampEstSymAvg = zeros(dataFileNum,channelNum);
|
||||
|
||||
angEstSymRaw = zeros(dataFileNum,symNum-1,channelNum);
|
||||
angEstSymMin = zeros(dataFileNum,channelNum);
|
||||
angEstSymMax = zeros(dataFileNum,channelNum);
|
||||
angEstSymAvg = zeros(dataFileNum,channelNum);
|
||||
|
||||
ampEstSymRawList = strings(dataFileNum*(symNum-1)+1,channelNum+1);
|
||||
ampEstSymRawList(1,:) = ["Amp Raw Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
|
||||
angEstSymRawList = strings(dataFileNum*(symNum-1)+1,channelNum+1);
|
||||
angEstSymRawList(1,:) = ["Angle Raw Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
|
||||
desiredPntIndexList = strings(dataFileNum*(symNum-1)+1,channelNum+1);
|
||||
desiredPntIndexList(1,:) = ["Chip Index", "ch1", "ch2", "ch3", "ch4"];
|
||||
|
||||
for data_num = 1:dataFileNum
|
||||
% read data
|
||||
rawData = readmatrix(dataFile(data_num));
|
||||
disp(dataFile(data_num));
|
||||
seqRx(:,1) = (rawData(:, 4) + 1i*rawData(:, 5)).';
|
||||
seqRx(:,2) = (rawData(:, 6) + 1i*rawData(:, 7)).';
|
||||
seqRx(:,3) = (rawData(:, 8) + 1i*rawData(:, 9)).';
|
||||
seqRx(:,4) = (rawData(:,10) + 1i*rawData(:,11)).';
|
||||
|
||||
% search for frequency shift
|
||||
for ch_num = 1:channelNum
|
||||
for freq_num = 1:length(freqRange)
|
||||
% multiply two symbols with carrier
|
||||
data_cxr = seqRx(1:2*chipLen*interp,ch_num).*exp(1i*2*pi* ...
|
||||
freqRange(freq_num)/fs*(0:2*chipLen*interp-1)');
|
||||
% convolve multiplied data with pn sequence, without zero-padded results
|
||||
data_dmf = conv(data_cxr, kron(flip(PRBS7_polar),ones(interp,1)),'valid');
|
||||
% peak search
|
||||
freqDmfPeak(data_num,freq_num) = max(data_dmf(1:end-1));
|
||||
end
|
||||
freqTarget(data_num,ch_num) = freqRange(freqDmfPeak(data_num,:) == max(freqDmfPeak(data_num,:)));
|
||||
end
|
||||
|
||||
% phase amplitude analysis
|
||||
for ch_num = 1:channelNum
|
||||
seqRxCxr = seqRx(:,ch_num).*exp(1i*2*pi*freqTarget(1)/fs*(0:dataLen-1)');
|
||||
seqRxCxrCorr = conv(seqRxCxr,kron(flip(PRBS7_polar),ones(interp,1)),'valid');
|
||||
seqRxCxrCorrSplit = reshape(seqRxCxrCorr(1:end-1),chipLen*interp, ...
|
||||
symNum-1);
|
||||
|
||||
desiredPntIndex(data_num,:,ch_num) = find(abs(seqRxCxrCorrSplit) == max(abs(seqRxCxrCorrSplit))) - 1024*(0:symNum-2)';
|
||||
desiredPnt(data_num,:,ch_num) = seqRxCxrCorrSplit(abs(seqRxCxrCorrSplit) == max(abs(seqRxCxrCorrSplit)));
|
||||
|
||||
ampEstSymRaw(data_num,:,ch_num) = abs(desiredPnt(data_num,:,ch_num))./abs(desiredPnt(data_num,:,1));
|
||||
angEstSymRaw(data_num,:,ch_num) = mod((angle(desiredPnt(data_num,:,ch_num))-angle(desiredPnt(data_num,:,1)))/pi*180,360);
|
||||
|
||||
ampEstSymMin(data_num,ch_num) = min(ampEstSymRaw(data_num,:,ch_num));
|
||||
ampEstSymMax(data_num,ch_num) = max(ampEstSymRaw(data_num,:,ch_num));
|
||||
ampEstSymAvg(data_num,ch_num) = mean(ampEstSymRaw(data_num,:,ch_num));
|
||||
|
||||
angEstSymMin(data_num,ch_num) = min(angEstSymRaw(data_num,:,ch_num));
|
||||
angEstSymMax(data_num,ch_num) = max(angEstSymRaw(data_num,:,ch_num));
|
||||
angEstSymAvg(data_num,ch_num) = mean(angEstSymRaw(data_num,:,ch_num));
|
||||
end
|
||||
|
||||
desiredPntIndexList((data_num-1)*(symNum-1)+1+(1:symNum-1),1) = dataFile(data_num);
|
||||
desiredPntIndexList((data_num-1)*(symNum-1)+1+(1:symNum-1),2:end) = string(desiredPntIndex(data_num,:,:));
|
||||
|
||||
ampEstSymRawList((data_num-1)*(symNum-1)+1+(1:symNum-1),1) = dataFile(data_num);
|
||||
ampEstSymRawList((data_num-1)*(symNum-1)+1+(1:symNum-1),2:end) = string(ampEstSymRaw(data_num,:,:));
|
||||
|
||||
angEstSymRawList((data_num-1)*(symNum-1)+1+(1:symNum-1),1) = dataFile(data_num);
|
||||
angEstSymRawList((data_num-1)*(symNum-1)+1+(1:symNum-1),2:end) = string(angEstSymRaw(data_num,:,:));
|
||||
end
|
||||
|
||||
freqTargetRelative = freqTarget - freqTarget(:,1);
|
||||
|
||||
ampEstSymMaxList = strings(dataFileNum+1,channelNum+1);
|
||||
ampEstSymMinList = strings(dataFileNum+1,channelNum+1);
|
||||
ampEstSymAvgList = strings(dataFileNum+1,channelNum+1);
|
||||
ampEstSymMaxList(1,:) = ["Amp Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
ampEstSymMinList(1,:) = ["Amp Min Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
ampEstSymAvgList(1,:) = ["Amp Avg Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
ampEstSymMaxList(2:end,1) = dataFile;
|
||||
ampEstSymMinList(2:end,1) = dataFile;
|
||||
ampEstSymAvgList(2:end,1) = dataFile;
|
||||
ampEstSymMaxList(2:end,2:end) = string(ampEstSymMin);
|
||||
ampEstSymMinList(2:end,2:end) = string(ampEstSymMax);
|
||||
ampEstSymAvgList(2:end,2:end) = string(ampEstSymAvg);
|
||||
|
||||
angEstSymMaxList = strings(dataFileNum+1,channelNum+1);
|
||||
angEstSymMinList = strings(dataFileNum+1,channelNum+1);
|
||||
angEstSymAvgList = strings(dataFileNum+1,channelNum+1);
|
||||
angEstSymMaxList(1,:) = ["Angle Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angEstSymMinList(1,:) = ["Angle Min Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angEstSymAvgList(1,:) = ["Angle Avg Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angEstSymMaxList(2:end,1) = dataFile;
|
||||
angEstSymMinList(2:end,1) = dataFile;
|
||||
angEstSymAvgList(2:end,1) = dataFile;
|
||||
angEstSymMaxList(2:end,2:end) = string(angEstSymMin);
|
||||
angEstSymMinList(2:end,2:end) = string(angEstSymMax);
|
||||
angEstSymAvgList(2:end,2:end) = string(angEstSymAvg);
|
||||
|
||||
%% figures
|
||||
figure(1);
|
||||
|
||||
subplot(121);
|
||||
plot(ampEstSymAvg);
|
||||
legend({"ch1","ch2","ch3","ch4"});
|
||||
title("Amplitude Estimation");
|
||||
ylim([min(ampEstSymAvg,[],'all')-0.2,max(ampEstSymAvg,[],'all')+0.2]);
|
||||
grid on; grid minor;
|
||||
|
||||
subplot(122);
|
||||
plot(angEstSymAvg);
|
||||
legend({"ch1","ch2","ch3","ch4"});
|
||||
title("Angle Estimation");
|
||||
ylim([-10,370]);
|
||||
grid on; grid minor;
|
||||
@@ -109,7 +109,7 @@ for data_num = 1:dataFileNum
|
||||
% convolve multiplied data with pn sequence, without zero-padded results
|
||||
data_dmf = conv(data_cxr, kron(flip(PRBS7_polar),ones(interp,1)),'valid');
|
||||
% peak search
|
||||
freqDmfPeak(data_num,freq_num) = max(data_dmf(1:end-1));
|
||||
freqDmfPeak(data_num,freq_num) = max(abs(data_dmf(1:end-1)));
|
||||
end
|
||||
freqTarget(data_num,ch_num) = freqRange(freqDmfPeak(data_num,:) == ...
|
||||
max(freqDmfPeak(data_num,:)));
|
||||
|
||||
Binary file not shown.
+74
@@ -0,0 +1,74 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rf_auto_control your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [31:0] probe1
|
||||
.probe2(probe2), // input wire [31:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5) // input wire [7:0] probe5
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rf_auto_control when simulating
|
||||
// the core, ila_rf_auto_control. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Thu May 11 11:37:56 2023
|
||||
// Host : Gatsby running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// C:/Workspce/814/josh/duifei_online_acq_par_20230510.xpr/project/project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.v
|
||||
// Design : ila_rf_auto_control
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rf_auto_control(clk, probe0, probe1, probe2, probe3, probe4, probe5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [31:0]probe1;
|
||||
input [31:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [7:0]probe5;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Thu May 11 11:37:56 2023
|
||||
-- Host : Gatsby running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- C:/Workspce/814/josh/duifei_online_acq_par_20230510.xpr/project/project.runs/ila_rf_auto_control_synth_1/ila_rf_auto_control_stub.vhdl
|
||||
-- Design : ila_rf_auto_control
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rf_auto_control is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rf_auto_control;
|
||||
|
||||
architecture stub of ila_rf_auto_control is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[31:0],probe2[31:0],probe3[0:0],probe4[0:0],probe5[7:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rf_auto_control (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [31 : 0] probe1;
|
||||
input [31 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [7 : 0] probe5;
|
||||
|
||||
|
||||
endmodule
|
||||
+2
-2
@@ -93,8 +93,8 @@ output reg [0 : 0] probe_out13 = 'h0 ;
|
||||
output reg [0 : 0] probe_out14 = 'h0 ;
|
||||
output reg [0 : 0] probe_out15 = 'h0 ;
|
||||
output reg [0 : 0] probe_out16 = 'h0 ;
|
||||
output reg [15 : 0] probe_out17 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out18 = 'h0000 ;
|
||||
output reg [31 : 0] probe_out17 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out18 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out19 = 'h00000000 ;
|
||||
output reg [31 : 0] probe_out20 = 'h00000000 ;
|
||||
|
||||
|
||||
+2
-2
@@ -75,8 +75,8 @@ vio_rfcontrl your_instance_name (
|
||||
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
|
||||
.probe_out15(probe_out15), // output wire [0 : 0] probe_out15
|
||||
.probe_out16(probe_out16), // output wire [0 : 0] probe_out16
|
||||
.probe_out17(probe_out17), // output wire [15 : 0] probe_out17
|
||||
.probe_out18(probe_out18), // output wire [15 : 0] probe_out18
|
||||
.probe_out17(probe_out17), // output wire [31 : 0] probe_out17
|
||||
.probe_out18(probe_out18), // output wire [31 : 0] probe_out18
|
||||
.probe_out19(probe_out19), // output wire [31 : 0] probe_out19
|
||||
.probe_out20(probe_out20) // output wire [31 : 0] probe_out20
|
||||
);
|
||||
|
||||
+2
-2
@@ -74,8 +74,8 @@ COMPONENT vio_rfcontrl
|
||||
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out17 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out18 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+4
-4
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed May 10 18:20:13 2023
|
||||
// Date : Thu May 11 18:37:07 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||
@@ -18,7 +18,7 @@ module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15,
|
||||
probe_out16, probe_out17, probe_out18, probe_out19, probe_out20)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]" */;
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */;
|
||||
input clk;
|
||||
input [15:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
@@ -39,8 +39,8 @@ module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0,
|
||||
output [0:0]probe_out14;
|
||||
output [0:0]probe_out15;
|
||||
output [0:0]probe_out16;
|
||||
output [15:0]probe_out17;
|
||||
output [15:0]probe_out18;
|
||||
output [31:0]probe_out17;
|
||||
output [31:0]probe_out18;
|
||||
output [31:0]probe_out19;
|
||||
output [31:0]probe_out20;
|
||||
endmodule
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed May 10 18:20:13 2023
|
||||
-- Date : Thu May 11 18:37:07 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||
@@ -34,8 +34,8 @@ entity vio_rfcontrl is
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out18 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
@@ -46,7 +46,7 @@ architecture stub of vio_rfcontrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu May 11 18:35:46 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_rf_auto_control.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_rf_auto_control.sh' script.
|
||||
|
||||
./ila_rf_auto_control.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_rf_auto_control.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_rf_auto_control.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_auto_control/hdl/verilog" \
|
||||
"../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_auto_control/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_auto_control/hdl/verilog"
|
||||
ila_rf_auto_control.v,verilog,xil_defaultlib,../../../ip/ila_rf_auto_control/sim/ila_rf_auto_control.v,incdir="../../../ip/ila_rf_auto_control/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_rf_auto_control.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu May 11 18:35:46 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_rf_auto_control.sh [-help]
|
||||
# usage: ila_rf_auto_control.sh [-lib_map_path]
|
||||
# usage: ila_rf_auto_control.sh [-noclean_files]
|
||||
# usage: ila_rf_auto_control.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_rf_auto_control.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_rf_auto_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_auto_control.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_auto_control.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_rf_auto_control.sh [-help]\n\
|
||||
Usage: ila_rf_auto_control.sh [-lib_map_path]\n\
|
||||
Usage: ila_rf_auto_control.sh [-reset_run]\n\
|
||||
Usage: ila_rf_auto_control.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+ila_rf_auto_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rf_auto_control xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {ila_rf_auto_control.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user