diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 02f71faa..cb488107 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,6 +1,6 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3331:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3831:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3832:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:36:00:00 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--- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,12 +1,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:39:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:3132:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:3134:00:00 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a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index f8e9d3e5..7e694a78 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:20 +6d6f64655f636f756e7465727c4755494d6f6465:21 eof: diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 4324c15f..c6336654 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,19 +18,19 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -44,33 +44,34 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + + - + - + - +
diff --git a/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix b/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix new file mode 100644 index 00000000..a0186288 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:48026ed1469063239a2169e0755ab2e7dcdf01aae68b598adaa97db8ffa398ca +size 29161992 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo new file mode 100644 index 00000000..cb2a2aa2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_rx_data_cnt your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [11:0] probe0 + .probe1(probe1), // input wire [11:0] probe1 + .probe2(probe2), // input wire [11:0] probe2 + .probe3(probe3), // input wire [11:0] probe3 + .probe4(probe4), // input wire [11:0] probe4 + .probe5(probe5), // input wire [11:0] probe5 + .probe6(probe6), // input wire [11:0] probe6 + .probe7(probe7), // input wire [11:0] probe7 + .probe8(probe8), // input wire [11:0] probe8 + .probe9(probe9) // input wire [9:0] probe9 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_rx_data_cnt when simulating +// the core, ila_rx_data_cnt. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v new file mode 100644 index 00000000..a4adeba4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c06d768c3fffa219f88e077f580f26ef5604b6a1f307543b6e430d4db7dcdfc6 +size 4423015 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl new file mode 100644 index 00000000..ece33838 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3d7ea2a94adf194396a25c01706e4c33015f8e1f88b084b194c7d0f65cb791df +size 6609619 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v new file mode 100644 index 00000000..382c80fb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed May 10 18:23:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [9:0]probe9; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl new file mode 100644 index 00000000..d7728a4f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed May 10 18:23:01 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rx_data_cnt is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + +end ila_rx_data_cnt; + +architecture stub of ila_rx_data_cnt is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v new file mode 100644 index 00000000..41289664 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_rx_data_cnt ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5, +probe6, +probe7, +probe8, +probe9 +); + +input clk; + + +input [11 : 0] probe0; +input [11 : 0] probe1; +input [11 : 0] probe2; +input [11 : 0] probe3; +input [11 : 0] probe4; +input [11 : 0] probe5; +input [11 : 0] probe6; +input [11 : 0] probe7; +input [11 : 0] probe8; +input [9 : 0] probe9; + + +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v deleted file mode 100644 index 0673f57f..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/hdl/vio_v3_0_20_vio_include.v +++ /dev/null @@ -1,283 +0,0 @@ -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) -`pragma protect key_block -GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx -XWe4lBDDrw== - -`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH -9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c -eVhT3XSIJDvufMyiJUc= - -`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit -pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX -LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 -5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a -sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== - -`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn -6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 -MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc -v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a -4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== - -`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v -ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX -cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC -xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa -draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv -j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO -R19uHYIhWP+7IpmjTiQ= - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM -kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV -cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 -7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 -mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) -`pragma protect data_block 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; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo index ae201a7c..1866f60b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo @@ -60,7 +60,8 @@ vio_freq_comp your_instance_name ( .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 .probe_out1(probe_out1), // output wire [7 : 0] probe_out1 .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 - .probe_out3(probe_out3) // output wire [31 : 0] probe_out3 + .probe_out3(probe_out3), // output wire [31 : 0] probe_out3 + .probe_out4(probe_out4) // output wire [0 : 0] probe_out4 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho index 72f0bda5..262db931 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho @@ -59,7 +59,8 @@ COMPONENT vio_freq_comp probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -75,7 +76,8 @@ your_instance_name : vio_freq_comp probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, - probe_out3 => probe_out3 + probe_out3 => probe_out3, + probe_out4 => probe_out4 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v index daabb4af..ee0fa2ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c34539843f7fa4c5906209eef95783110cbf58f52a239344578ff4d3cfabfab3 -size 347789 +oid sha256:194adcb2584460a0c49f443e10ff808afc50b94c08121d3b2a8799894a5cd8f0 +size 356709 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl index ced3f879..8ba3790d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab1d7e314e1d93fce13386e493892ccc6fd24d37980345a48e6d890ba0520334 -size 625987 +oid sha256:284e403615e7267061792d90faf87676725b1d0f13edce936f4f9ad73d9189dd +size 636069 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v index 85124391..4f7d1942 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 13:15:24 2023 +// Date : Wed May 10 18:23:14 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v // Design : vio_freq_comp // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -15,12 +15,13 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + probe_out2, probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]" */; input clk; input [0:0]probe_in0; output [0:0]probe_out0; output [7:0]probe_out1; output [0:0]probe_out2; output [31:0]probe_out3; + output [0:0]probe_out4; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl index 015c276d..c08c2d99 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 13:15:24 2023 +-- Date : Wed May 10 18:23:14 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl -- Design : vio_freq_comp -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -19,7 +19,8 @@ entity vio_freq_comp is probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_freq_comp; @@ -28,7 +29,7 @@ architecture stub of vio_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v deleted file mode 100644 index 0673f57f..00000000 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/hdl/vio_v3_0_20_vio_include.v +++ /dev/null @@ -1,283 +0,0 @@ -`pragma protect begin_protected -`pragma protect version = 1 -`pragma protect encrypt_agent = "XILINX" -`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" -`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) -`pragma protect key_block -GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx -XWe4lBDDrw== - -`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH -9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c -eVhT3XSIJDvufMyiJUc= - -`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit -pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX -LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3 -5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a -sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ== - -`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn -6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49 -MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc -v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a -4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A== - -`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v -ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX -cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC -xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa -draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) -`pragma protect key_block -ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv -j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO -R19uHYIhWP+7IpmjTiQ= - -`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) -`pragma protect key_block -AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM -kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV -cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 -7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 -mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== - -`pragma protect data_method = "AES128-CBC" -`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) -`pragma protect data_block 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probe_in1; output reg [0 : 0] probe_out0 = 'h0 ; output reg [0 : 0] probe_out1 = 'h0 ; @@ -90,6 +94,9 @@ output reg [0 : 0] probe_out14 = 'h0 ; output reg [0 : 0] probe_out15 = 'h0 ; output reg [0 : 0] probe_out16 = 'h0 ; output reg [15 : 0] probe_out17 = 'h0000 ; +output reg [15 : 0] probe_out18 = 'h0000 ; +output reg [31 : 0] probe_out19 = 'h00000000 ; +output reg [31 : 0] probe_out20 = 'h00000000 ; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo index 59ec6ab1..aafe0308 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.veo @@ -57,6 +57,7 @@ vio_rfcontrl your_instance_name ( .clk(clk), // input wire clk .probe_in0(probe_in0), // input wire [15 : 0] probe_in0 + .probe_in1(probe_in1), // input wire [0 : 0] probe_in1 .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 .probe_out2(probe_out2), // output wire [15 : 0] probe_out2 @@ -74,7 +75,10 @@ vio_rfcontrl your_instance_name ( .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 .probe_out15(probe_out15), // output wire [0 : 0] probe_out15 .probe_out16(probe_out16), // output wire [0 : 0] probe_out16 - .probe_out17(probe_out17) // output wire [15 : 0] probe_out17 + .probe_out17(probe_out17), // output wire [15 : 0] probe_out17 + .probe_out18(probe_out18), // output wire [15 : 0] probe_out18 + .probe_out19(probe_out19), // output wire [31 : 0] probe_out19 + .probe_out20(probe_out20) // output wire [31 : 0] probe_out20 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho index 8e3710c3..838a0aed 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl.vho @@ -56,6 +56,7 @@ COMPONENT vio_rfcontrl PORT ( clk : IN STD_LOGIC; probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -73,7 +74,10 @@ COMPONENT vio_rfcontrl probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -86,6 +90,7 @@ your_instance_name : vio_rfcontrl PORT MAP ( clk => clk, probe_in0 => probe_in0, + probe_in1 => probe_in1, probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, @@ -103,7 +108,10 @@ your_instance_name : vio_rfcontrl probe_out14 => probe_out14, probe_out15 => probe_out15, probe_out16 => probe_out16, - probe_out17 => probe_out17 + probe_out17 => probe_out17, + probe_out18 => probe_out18, + probe_out19 => probe_out19, + probe_out20 => probe_out20 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v index 045f923b..69cd8916 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:795e37fa5092bed76bd5666e05cb723247face647baf3ad8fae43fc62a1b160e -size 429585 +oid sha256:4f1a9f92eb36bfc1a930fea2d1f29f4906f55062c43bfb8ba026dcd0c6c7688e +size 498496 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl index 947c8fdd..be83dab8 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f9b2adcaf809ac070ceed79970f8ed6d58a91149d1358bbad5cf3844870fef4 -size 743518 +oid sha256:c1a367565775776ceb2634eb84be77f5f08c895752497ff1c94169a9551b7a83 +size 836814 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v index 1d32ada2..b537fe6d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 13:15:25 2023 +// Date : Wed May 10 18:20:13 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v // Design : vio_rfcontrl // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -14,13 +14,14 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, - probe_out17) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; +module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]" */; input clk; input [15:0]probe_in0; + input [0:0]probe_in1; output [0:0]probe_out0; output [0:0]probe_out1; output [15:0]probe_out2; @@ -39,4 +40,7 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, output [0:0]probe_out15; output [0:0]probe_out16; output [15:0]probe_out17; + output [15:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl index ba0a2f31..cf20e31f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 13:15:25 2023 +-- Date : Wed May 10 18:20:13 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl -- Design : vio_rfcontrl -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -16,6 +16,7 @@ entity vio_rfcontrl is Port ( clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); @@ -33,7 +34,10 @@ entity vio_rfcontrl is probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end vio_rfcontrl; @@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do new file mode 100644 index 00000000..cec194d4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh new file mode 100755 index 00000000..18c58659 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do new file mode 100644 index 00000000..068bbc78 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rx_data_cnt.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt new file mode 100644 index 00000000..9e00f322 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh new file mode 100755 index 00000000..7eb583cd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/ila_rx_data_cnt.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rx_data_cnt \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f new file mode 100644 index 00000000..2fc025f3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do new file mode 100644 index 00000000..9fc0a8d5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh new file mode 100755 index 00000000..1b16d206 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do new file mode 100644 index 00000000..17f1eccd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rx_data_cnt.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do new file mode 100644 index 00000000..1cdeccee --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do new file mode 100644 index 00000000..7d20aec2 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_opt diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh new file mode 100755 index 00000000..1777c3c9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do new file mode 100644 index 00000000..11bbded3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib ila_rx_data_cnt_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rx_data_cnt.udo} + +run -all + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do new file mode 100644 index 00000000..39317df9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh new file mode 100755 index 00000000..f1729257 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.udo b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/ila_rx_data_cnt.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do new file mode 100644 index 00000000..068bbc78 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rx_data_cnt.udo} + +run -all + +endsim + +quit -force diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh new file mode 100755 index 00000000..5c8fe4aa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/ila_rx_data_cnt.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rx_data_cnt/hdl/verilog" \ + "$ref_dir/../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_simv +} + +# RUN_STEP: +simulate() +{ + ./ila_rx_data_cnt_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ila_rx_data_cnt_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rx_data_cnt_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt new file mode 100644 index 00000000..9e00f322 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt new file mode 100644 index 00000000..bceaf25a --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh new file mode 100755 index 00000000..e46316e9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/ila_rx_data_cnt.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rx_data_cnt \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f new file mode 100644 index 00000000..fd1b270c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt new file mode 100644 index 00000000..381b6fc0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed May 10 18:21:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rx_data_cnt.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rx_data_cnt.sh' script. + +./ila_rx_data_cnt.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rx_data_cnt.sh -noclean_files + +For more information on the script, please type './ila_rx_data_cnt.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt new file mode 100644 index 00000000..0689f6df --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh new file mode 100755 index 00000000..3fd6a016 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/ila_rx_data_cnt.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rx_data_cnt.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed May 10 18:21:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rx_data_cnt.sh [-help] +# usage: ila_rx_data_cnt.sh [-lib_map_path] +# usage: ila_rx_data_cnt.sh [-noclean_files] +# usage: ila_rx_data_cnt.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rx_data_cnt xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_rx_data_cnt -key {Behavioral:sim_1:Functional:ila_rx_data_cnt} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rx_data_cnt.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rx_data_cnt.sh [-help]\n\ +Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\ +Usage: ila_rx_data_cnt.sh [-reset_run]\n\ +Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj new file mode 100644 index 00000000..23d83e79 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/ila_rx_data_cnt/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_rx_data_cnt/hdl/verilog" \ +"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh index aa6531a2..0b890e67 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/activehdl/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt index 3ae276e6..4bb5201b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh index aa2d4acd..f7711f96 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/ies/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh index d65d58fe..4c7accea 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/modelsim/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh index f42833f0..43f2cee1 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/questa/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -105,7 +105,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh index e88ba15e..c92b3607 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/riviera/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh index ed68a199..1458ba77 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/vcs/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt index 3ae276e6..4bb5201b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh index c79679fc..eb04b277 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xcelium/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt index 9a520055..87b328ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:17 CST 2023 +# Generated by export_simulation on Wed May 10 18:22:56 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh index 4b6f3e20..3b3fee7e 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_freq_comp/xsim/vio_freq_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:17 CST 2023 +# Generated by Vivado on Wed May 10 18:22:56 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh index 54569c04..c50bce84 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/activehdl/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt index 74621eb6..c6061011 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh index bbcc6280..d2051f16 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/ies/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh index 02af7064..6a51d7d9 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/modelsim/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh index 33725865..d79d5607 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/questa/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -105,7 +105,7 @@ copy_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh index 96e81713..235ce32e 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/riviera/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -96,7 +96,7 @@ map_setup_file() if [[ ($1 != "") ]]; then lib_map_path="$1" else - lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" fi if [[ ($lib_map_path != "") ]]; then src_file="$lib_map_path/$file" diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh index 83e65030..86b66b0c 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/vcs/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt index 74621eb6..c6061011 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh index 9871883f..bd17b9ab 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xcelium/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt index efc0100d..c8aaef38 100644 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon May 08 13:15:28 CST 2023 +# Generated by export_simulation on Wed May 10 18:19:54 CST 2023 # ################################################################################ diff --git a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh index f55e95a1..b527fc93 100755 --- a/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh +++ b/projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/vio_rfcontrl/xsim/vio_rfcontrl.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon May 08 13:15:28 CST 2023 +# Generated by Vivado on Wed May 10 18:19:54 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/3562b3f5445704f9.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/3562b3f5445704f9.xci new file mode 100644 index 00000000..bdf6e9d3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/3562b3f5445704f9.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 3562b3f5445704f9 + 0 + + + vio_rfcontrl + + + 100000000 + 0 + 1 + 2 + 21 + 16 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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sha256:262f406731be71b3fde7aaca8cef26f48aeb2034e99b8f53bf812df52978760c +size 231961 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.v new file mode 100755 index 00000000..6aeafa2d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:efd125c8d56cf0a07789746e0faba267b61f7add01ac06e90368881765922632 +size 499729 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.vhdl new file mode 100755 index 00000000..b1c586e5 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4db3c33436ee9e57245f7219d07512fbfbbaa4e85e0c3e4c22736b6e5b374a85 +size 878217 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.v new file mode 100755 index 00000000..bbe74689 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.v @@ -0,0 +1,46 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed May 10 18:20:12 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v +// Design : vio_rfcontrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]" */; + input clk; + input [15:0]probe_in0; + input [0:0]probe_in1; + output [0:0]probe_out0; + output [0:0]probe_out1; + output [15:0]probe_out2; + output [7:0]probe_out3; + output [3:0]probe_out4; + output [3:0]probe_out5; + output [3:0]probe_out6; + output [3:0]probe_out7; + output [7:0]probe_out8; + output [7:0]probe_out9; + output [15:0]probe_out10; + output [15:0]probe_out11; + output [15:0]probe_out12; + output [0:0]probe_out13; + output [0:0]probe_out14; + output [0:0]probe_out15; + output [0:0]probe_out16; + output [15:0]probe_out17; + output [15:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.vhdl new file mode 100755 index 00000000..5c6a01d1 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/3562b3f5445704f9/vio_rfcontrl_stub.vhdl @@ -0,0 +1,53 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed May 10 18:20:12 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl +-- Design : vio_rfcontrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/67483215c55000dc.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/67483215c55000dc.xci new file mode 100644 index 00000000..cb210e71 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/67483215c55000dc.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 67483215c55000dc + 0 + + + vio_freq_comp + + + 100000000 + 0 + 1 + 1 + 5 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + vio_freq_comp + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 67483215c55000dc + 9a10a187 + 13 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp.dcp new file mode 100644 index 00000000..c1fbb111 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cc4e2cad5a26b4f7de9eded6c59f729570df218f7240674e353725391c7a67ff +size 146636 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.v new file mode 100755 index 00000000..2d46c4c3 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8a26031d193e934fb51c99f3c0484df9c842a49776418105e0c807c9b6006488 +size 356990 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.vhdl new file mode 100755 index 00000000..998f56fa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d0c9ff900edd8a652953ba70b3bc6a2c5d83d46bcebef8baa92032595b4a51c6 +size 673762 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.v new file mode 100755 index 00000000..c32c2575 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.v @@ -0,0 +1,27 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed May 10 18:23:13 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.v +// Design : vio_freq_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]" */; + input clk; + input [0:0]probe_in0; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [0:0]probe_out2; + output [31:0]probe_out3; + output [0:0]probe_out4; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.vhdl new file mode 100755 index 00000000..6dd5ca2c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/67483215c55000dc/vio_freq_comp_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed May 10 18:23:13 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_freq_comp_stub.vhdl +-- Design : vio_freq_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/b21318091042a7f7.xci b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/b21318091042a7f7.xci new file mode 100644 index 00000000..14d87cea --- /dev/null +++ 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.v new file mode 100755 index 00000000..7853f26f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed May 10 18:22:59 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [9:0]probe9; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.vhdl new file mode 100755 index 00000000..cc4bdd48 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/b21318091042a7f7/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed May 10 18:22:59 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index f4ff7423..30806a7e 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,12 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3138:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173657265706f72747461625f726572756e:31:00:00 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a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index c7c2fb69..0161c5dc 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:5 +6d6f64655f636f756e7465727c4755494d6f6465:6 eof: diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 1a98dc4f..c85a32a6 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f667265715f636f6d70:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f667265715f636f6d70:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323130352e3639314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730302e3834304d42:00:00 +eof:1681585722 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index e5522ba8..f9fdaa18 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -20,25 +20,27 @@ This means code written to parse this file will need to be revisited each subseq + - + - + - - + + + - - + + @@ -57,22 +59,22 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - +
diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_10.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_10.xml new file mode 100644 index 00000000..81f8180e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml new file mode 100644 index 00000000..ff7ded0c --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml new file mode 100644 index 00000000..dda7de74 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml index b9861298..7ebd1fdc 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml index c7272869..c8e7e69f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - - - - - - + + + + + @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml index fb9c6d9c..7d1e6cf7 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - + + + - - - - diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.Vivado_Synthesis.queue.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..d487e6e9 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.end.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/__synthesis_is_complete__ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc new file mode 100644 index 00000000..96c7a4ac --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +# IP: The module: 'ila_rx_data_cnt' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +# IP: The module: 'ila_rx_data_cnt' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rx_data_cnt'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml new file mode 100644 index 00000000..fea8667e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt new file mode 100644 index 00000000..fe0a3fdd --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp new file mode 100644 index 00000000..3d294f0e --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b1fbec0928300dd59b33473e964a1f9c285ab824a4a84ae03d23fb3f1b25b884 +size 2129582 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl new file mode 100644 index 00000000..3453f930 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.tcl @@ -0,0 +1,159 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci +set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1 -new_name ila_rx_data_cnt -ip [get_ips ila_rx_data_cnt]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top ila_rx_data_cnt -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix ila_rx_data_cnt_ ila_rx_data_cnt.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.v + lappend ipCachedFiles ila_rx_data_cnt_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_stub.vhdl + lappend ipCachedFiles ila_rx_data_cnt_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_sim_netlist.v + lappend ipCachedFiles ila_rx_data_cnt_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rx_data_cnt_sim_netlist.vhdl + lappend ipCachedFiles ila_rx_data_cnt_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp ila_rx_data_cnt.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_rx_data_cnt] +} + +rename_ref -prefix_all ila_rx_data_cnt_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef ila_rx_data_cnt.dcp +create_report "ila_rx_data_cnt_synth_1_synth_report_utilization_0" "report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] + +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds new file mode 100644 index 00000000..d987b759 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds @@ -0,0 +1,3204 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Wed May 10 18:21:39 2023 +# Process ID: 227994 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1 +# Command line: vivado -log ila_rx_data_cnt.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.jou +#----------------------------------------------------------- +source ila_rx_data_cnt.tcl -notrace +Command: synth_design -top ila_rx_data_cnt -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 228123 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1883.074 ; gain = 161.719 ; free physical = 508 ; free virtual = 52264 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'ila_rx_data_cnt' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] +INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (12#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (13#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (25#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (27#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (32#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:3227] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rx_data_cnt does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:116] +INFO: [Synth 8-6155] done synthesizing module 'ila_rx_data_cnt' (52#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/synth/ila_rx_data_cnt.v:84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_RST[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MEM_LAT_RST +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port MUX_REGCE[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port WE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[12] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[11] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[10] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[9] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port ADDR_IN[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[119] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[118] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[117] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[116] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[115] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[114] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[113] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[112] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[111] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[110] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[109] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[108] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[107] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[106] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[105] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[104] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[103] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[102] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[101] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[100] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[99] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[98] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[97] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[96] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[95] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[94] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[93] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[92] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[91] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[90] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[89] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[88] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[87] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[86] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[85] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[83] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[82] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[81] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[80] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[79] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[78] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[77] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[76] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[75] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[74] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[73] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[72] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[71] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[70] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[69] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[68] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[67] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[66] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[65] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[64] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[63] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[62] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[61] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[60] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[59] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[58] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[57] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[56] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[55] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[54] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[53] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[52] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[51] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[50] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[49] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[48] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[47] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[46] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[45] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[44] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[43] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[42] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[41] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[40] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[39] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[38] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 has unconnected port SBITERRIN[37] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:39 ; elapsed = 00:00:49 . Memory (MB): peak = 2259.770 ; gain = 538.414 ; free physical = 985 ; free virtual = 52507 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2259.770 ; gain = 538.414 ; free physical = 1000 ; free virtual = 52527 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2259.770 ; gain = 538.414 ; free physical = 1000 ; free virtual = 52527 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 864 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.613 ; gain = 0.000 ; free physical = 788 ; free virtual = 52362 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 636 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances + CFGLUT5 => SRLC32E: 56 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2356.613 ; gain = 0.000 ; free physical = 785 ; free virtual = 52359 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:44 ; elapsed = 00:00:55 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 889 ; free virtual = 52481 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:44 ; elapsed = 00:00:55 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 889 ; free virtual = 52481 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:00:55 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 891 ; free virtual = 52483 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized55' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized56' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized11' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized12' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized13' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized14' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized15' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized16' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized17' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized18' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized19' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized20' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized21' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized22' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized23' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized24' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized25' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized26' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized27' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized28' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized29' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized30' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized31' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized32' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized33' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized34' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized35' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized36' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized37' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized38' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized39' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized40' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized41' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized42' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized43' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized44' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized45' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized46' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized47' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized48' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized49' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized50' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized51' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized52' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized53' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized54' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 848 ; free virtual = 52463 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 4 + 2 Input 13 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 4 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 58 + 2 Input 3 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 72 + 2 Input 1 Bit XORs := 4 ++---Registers : + 1024 Bit Registers := 2 + 128 Bit Registers := 2 + 118 Bit Registers := 9 + 33 Bit Registers := 2 + 32 Bit Registers := 9 + 24 Bit Registers := 1 + 20 Bit Registers := 33 + 17 Bit Registers := 2 + 16 Bit Registers := 216 + 13 Bit Registers := 9 + 12 Bit Registers := 36 + 10 Bit Registers := 4 + 9 Bit Registers := 1 + 8 Bit Registers := 1 + 7 Bit Registers := 5 + 6 Bit Registers := 2 + 4 Bit Registers := 61 + 3 Bit Registers := 1 + 2 Bit Registers := 6 + 1 Bit Registers := 381 ++---Muxes : + 2 Input 119 Bit Muxes := 2 + 2 Input 118 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 12 + 2 Input 16 Bit Muxes := 72 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 58 + 3 Input 15 Bit Muxes := 1 + 8 Input 13 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 176 + 5 Input 4 Bit Muxes := 58 + 2 Input 3 Bit Muxes := 58 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 6 + 2 Input 1 Bit Muxes := 351 + 4 Input 1 Bit Muxes := 2 + 3 Input 1 Bit Muxes := 58 + 9 Input 1 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module ila_v6_2_9_generic_counter +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 2 ++---Muxes : + 2 Input 32 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 2 +Module ila_v6_2_9_ila_adv_trigger_sequencer +Detailed RTL Component Info : ++---Adders : + 2 Input 7 Bit Adders := 2 ++---Registers : + 24 Bit Registers := 1 + 16 Bit Registers := 1 + 7 Bit Registers := 2 + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 10 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 9 + 4 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_fsm_memory_read +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 8 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized55 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 17 Bit Registers := 1 + 16 Bit Registers := 4 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg__parameterized39 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized40 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized54 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized55 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized56 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized57 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized58 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized59 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized60 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized61 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized62 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized63 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized64 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized65 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized56 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stream__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized0 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized2 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized7 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized8 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized9 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized11 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized12 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized13 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized14 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized15 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized16 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized17 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized18 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized19 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized20 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized21 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized22 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized23 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized24 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized25 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized26 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized27 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized28 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized29 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized30 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized31 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized32 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized33 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized34 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized35 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized36 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized37 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized38 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized39 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized40 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized41 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized42 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized43 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized44 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized45 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized46 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized47 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized48 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized49 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized50 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized51 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized52 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized53 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized54 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_register +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 1024 Bit Registers := 2 + 17 Bit Registers := 1 + 16 Bit Registers := 12 + 9 Bit Registers := 1 + 7 Bit Registers := 2 + 6 Bit Registers := 1 + 1 Bit Registers := 31 ++---Muxes : + 2 Input 16 Bit Muxes := 10 + 4 Input 16 Bit Muxes := 2 + 3 Input 16 Bit Muxes := 1 + 3 Input 15 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 13 + 9 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 20 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1 +Detailed RTL Component Info : ++---Registers : + 10 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ila_v6_2_9_ila_trigger +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_async_edge_xfer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_rising_edge_detection +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ila_v6_2_9_ila_reset_ctrl +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_cfglut7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay +Detailed RTL Component Info : ++---Registers : + 13 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_addrgen +Detailed RTL Component Info : ++---Registers : + 33 Bit Registers := 2 + 16 Bit Registers := 1 + 13 Bit Registers := 3 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 13 +Module ltlib_v1_0_0_cfglut6__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_cap_ctrl_legacy +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module blk_mem_gen_v8_4_3_bindec +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux +Detailed RTL Component Info : ++---Registers : + 13 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 119 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +Module blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 +Detailed RTL Component Info : ++---Registers : + 13 Bit Registers := 1 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 119 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 2 +Module ltlib_v1_0_0_generic_memrd +Detailed RTL Component Info : ++---Adders : + 2 Input 13 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 ++---Registers : + 128 Bit Registers := 1 + 13 Bit Registers := 1 + 7 Bit Registers := 1 + 4 Bit Registers := 2 + 3 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 8 Input 13 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +Module ila_v6_2_9_ila_core +Detailed RTL Component Info : ++---Registers : + 118 Bit Registers := 9 + 16 Bit Registers := 2 + 2 Bit Registers := 3 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 118 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 +Module ila_v6_2_9_ila +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\shift_reg0_reg[1023] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[14].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[12].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[10].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_a/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[3]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[16].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[18].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[9].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/CNT_WIDTH_STATUS[0].cnt_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs /\slaveRegDo_mux_1_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:52 ; elapsed = 00:01:04 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 689 ; free virtual = 52424 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 421 ; free virtual = 52189 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 469 ; free virtual = 52196 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ +|inst | ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg | User Attribute | 128 x 24 | RAM64M x 32 | ++------------+----------------------------------------------------+----------------+----------------------+---------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:01:09 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 452 ; free virtual = 52180 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:58 ; elapsed = 00:01:09 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 462 ; free virtual = 52180 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:58 ; elapsed = 00:01:09 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 461 ; free virtual = 52179 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 438 ; free virtual = 52163 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 438 ; free virtual = 52163 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 429 ; free virtual = 52157 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 429 ; free virtual = 52157 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|ila_v6_2_9_generic_counter | counter_load_i_reg[16] | 16 | 4 | NO | NO | YES | 4 | 0 | +|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 4 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][117] | 9 | 118 | NO | NO | YES | 118 | 0 | ++---------------------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 228| +|2 |CFGLUT5 | 636| +|3 |LUT1 | 90| +|4 |LUT2 | 111| +|5 |LUT3 | 378| +|6 |LUT4 | 558| +|7 |LUT5 | 254| +|8 |LUT6 | 1602| +|9 |MUXF7 | 135| +|10 |MUXF8 | 2| +|11 |RAM64M | 32| +|12 |RAMB18E1 | 1| +|13 |RAMB36E1 | 26| +|14 |SRL16E | 126| +|15 |SRLC16E | 2| +|16 |SRLC32E | 17| +|17 |FDRE | 4419| +|18 |FDSE | 9| ++------+---------+------+ + +Report Instance Areas: ++------+------------------------------------------------------------------------+-------------------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------------------------------------+-------------------------------------------------------------+------+ +|1 |top | | 8626| +|2 | inst |ila_v6_2_9_ila | 8626| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 8619| +|4 | \ADV_TRIG.u_adv_trig |ila_v6_2_9_ila_adv_trigger_sequencer | 185| +|5 | \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst |ila_v6_2_9_ila_fsm_memory_read | 52| +|6 | \COUNTER.u_count |ila_v6_2_9_ila_counter | 232| +|7 | \G_COUNTER[0].U_COUNTER |ila_v6_2_9_generic_counter__1 | 58| +|8 | \G_COUNTER[1].U_COUNTER |ila_v6_2_9_generic_counter__2 | 58| +|9 | \G_COUNTER[2].U_COUNTER |ila_v6_2_9_generic_counter__3 | 58| +|10 | \G_COUNTER[3].U_COUNTER |ila_v6_2_9_generic_counter | 58| +|11 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 149| +|12 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 149| +|13 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 149| +|14 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 149| +|15 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 149| +|16 | \bindec_a.bindec_inst_a |blk_mem_gen_v8_4_3_bindec | 2| +|17 | \has_mux_b.B |blk_mem_gen_v8_4_3_blk_mem_gen_mux__parameterized0 | 3| +|18 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|19 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|20 | \ramloop[10].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized9 | 10| +|21 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized9 | 10| +|22 | \ramloop[11].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized10 | 1| +|23 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized10 | 1| +|24 | \ramloop[12].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized11 | 10| +|25 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized11 | 10| +|26 | \ramloop[13].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized12 | 1| +|27 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized12 | 1| +|28 | \ramloop[14].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized13 | 10| +|29 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized13 | 10| +|30 | \ramloop[15].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized14 | 1| +|31 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized14 | 1| +|32 | \ramloop[16].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized15 | 10| +|33 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized15 | 10| +|34 | \ramloop[17].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized16 | 1| +|35 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized16 | 1| +|36 | \ramloop[18].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized17 | 10| +|37 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized17 | 10| +|38 | \ramloop[19].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized18 | 1| +|39 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized18 | 1| +|40 | \ramloop[1].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized0 | 1| +|41 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 | 1| +|42 | \ramloop[20].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized19 | 10| +|43 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized19 | 10| +|44 | \ramloop[21].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized20 | 1| +|45 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized20 | 1| +|46 | \ramloop[22].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized21 | 10| +|47 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized21 | 10| +|48 | \ramloop[23].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized22 | 1| +|49 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized22 | 1| +|50 | \ramloop[24].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized23 | 10| +|51 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized23 | 10| +|52 | \ramloop[25].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized24 | 1| +|53 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized24 | 1| +|54 | \ramloop[26].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized25 | 10| +|55 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized25 | 10| +|56 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 10| +|57 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 10| +|58 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| +|59 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| +|60 | \ramloop[4].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized3 | 10| +|61 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized3 | 10| +|62 | \ramloop[5].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized4 | 1| +|63 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized4 | 1| +|64 | \ramloop[6].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized5 | 10| +|65 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized5 | 10| +|66 | \ramloop[7].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized6 | 1| +|67 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized6 | 1| +|68 | \ramloop[8].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized7 | 10| +|69 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized7 | 10| +|70 | \ramloop[9].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized8 | 1| +|71 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized8 | 1| +|72 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 293| +|73 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|74 | U_NS0 |ltlib_v1_0_0_cfglut7 | 8| +|75 | U_NS1 |ltlib_v1_0_0_cfglut7_312 | 10| +|76 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 265| +|77 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|78 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 62| +|79 | U_SCE |ltlib_v1_0_0_cfglut4_319 | 1| +|80 | U_SCMPCE |ltlib_v1_0_0_cfglut5_320 | 1| +|81 | U_SCRST |ltlib_v1_0_0_cfglut6_321 | 3| +|82 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_322 | 25| +|83 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_323 | 25| +|84 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_324 | 12| +|85 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_325 | 5| +|86 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_326 | 5| +|87 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 60| +|88 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|89 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|90 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_313 | 1| +|91 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|92 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_315 | 12| +|93 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_316 | 12| +|94 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_317 | 5| +|95 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_318 | 5| +|96 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_314 | 25| +|97 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 25| +|98 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| +|99 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|100 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|101 | u_ila_regs |ila_v6_2_9_ila_register | 5885| +|102 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|103 | reg_890 |xsdbs_v1_0_2_reg__parameterized72 | 16| +|104 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_311 | 16| +|105 | \ADV_TRIG_STREAM.reg_stream_ffc |xsdbs_v1_0_2_reg_stream__parameterized0 | 25| +|106 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_310 | 21| +|107 | \ADV_TRIG_STREAM_READBACK.reg_stream_ffb |xsdbs_v1_0_2_reg_stream | 37| +|108 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_309 | 37| +|109 | \CNT.CNT_SRL[0].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized51 | 74| +|110 | \CNT.CNT_SRL[1].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized52 | 74| +|111 | \CNT.CNT_SRL[2].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized53 | 90| +|112 | \CNT.CNT_SRL[3].cnt_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized54 | 76| +|113 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 74| +|114 | \MU_SRL[10].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 74| +|115 | \MU_SRL[11].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized10 | 106| +|116 | \MU_SRL[12].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized11 | 74| +|117 | \MU_SRL[13].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized12 | 74| +|118 | \MU_SRL[14].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized13 | 74| +|119 | \MU_SRL[15].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized14 | 90| +|120 | \MU_SRL[16].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized15 | 74| +|121 | \MU_SRL[17].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized16 | 74| +|122 | \MU_SRL[18].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized17 | 74| +|123 | \MU_SRL[19].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized18 | 106| +|124 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 74| +|125 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 74| +|126 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 106| +|127 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 74| +|128 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 74| +|129 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 74| +|130 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 90| +|131 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 74| +|132 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 74| +|133 | \STRG_QUAL.qual_strg_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized55 | 90| +|134 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized19 | 74| +|135 | \TC_SRL[10].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized29 | 74| +|136 | \TC_SRL[11].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized30 | 106| +|137 | \TC_SRL[12].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized31 | 74| +|138 | \TC_SRL[13].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized32 | 74| +|139 | \TC_SRL[14].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized33 | 74| +|140 | \TC_SRL[15].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized34 | 90| +|141 | \TC_SRL[16].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized35 | 74| +|142 | \TC_SRL[17].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized36 | 74| +|143 | \TC_SRL[18].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized37 | 74| +|144 | \TC_SRL[19].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized38 | 106| +|145 | \TC_SRL[1].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized20 | 74| +|146 | \TC_SRL[20].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized39 | 74| +|147 | \TC_SRL[21].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized40 | 74| +|148 | \TC_SRL[22].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized41 | 74| +|149 | \TC_SRL[23].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized42 | 90| +|150 | \TC_SRL[24].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized43 | 74| +|151 | \TC_SRL[25].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized44 | 74| +|152 | \TC_SRL[26].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized45 | 74| +|153 | \TC_SRL[27].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized46 | 122| +|154 | \TC_SRL[28].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized47 | 74| +|155 | \TC_SRL[29].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized48 | 74| +|156 | \TC_SRL[2].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized21 | 74| +|157 | \TC_SRL[30].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized49 | 74| +|158 | \TC_SRL[31].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized50 | 90| +|159 | \TC_SRL[3].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized22 | 106| +|160 | \TC_SRL[4].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized23 | 74| +|161 | \TC_SRL[5].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized24 | 74| +|162 | \TC_SRL[6].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized25 | 74| +|163 | \TC_SRL[7].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized26 | 90| +|164 | \TC_SRL[8].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized27 | 74| +|165 | \TC_SRL[9].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized28 | 74| +|166 | reg_15 |xsdbs_v1_0_2_reg__parameterized54 | 34| +|167 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_308 | 34| +|168 | reg_16 |xsdbs_v1_0_2_reg__parameterized55 | 18| +|169 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_307 | 18| +|170 | reg_17 |xsdbs_v1_0_2_reg__parameterized56 | 32| +|171 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_306 | 32| +|172 | reg_18 |xsdbs_v1_0_2_reg__parameterized57 | 31| +|173 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_305 | 31| +|174 | reg_19 |xsdbs_v1_0_2_reg__parameterized58 | 17| +|175 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_304 | 17| +|176 | reg_1a |xsdbs_v1_0_2_reg__parameterized59 | 27| +|177 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 27| +|178 | reg_6 |xsdbs_v1_0_2_reg__parameterized39 | 24| +|179 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_303 | 24| +|180 | reg_7 |xsdbs_v1_0_2_reg__parameterized40 | 33| +|181 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 33| +|182 | reg_8 |xsdbs_v1_0_2_reg__parameterized41 | 7| +|183 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_302 | 7| +|184 | reg_80 |xsdbs_v1_0_2_reg__parameterized60 | 17| +|185 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2_301 | 17| +|186 | reg_81 |xsdbs_v1_0_2_reg__parameterized61 | 17| +|187 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_300 | 17| +|188 | reg_82 |xsdbs_v1_0_2_reg__parameterized62 | 17| +|189 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized2 | 17| +|190 | reg_83 |xsdbs_v1_0_2_reg__parameterized63 | 64| +|191 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_299 | 64| +|192 | reg_84 |xsdbs_v1_0_2_reg__parameterized64 | 21| +|193 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_298 | 21| +|194 | reg_85 |xsdbs_v1_0_2_reg__parameterized65 | 17| +|195 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_297 | 17| +|196 | reg_887 |xsdbs_v1_0_2_reg__parameterized67 | 3| +|197 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_296 | 3| +|198 | reg_88d |xsdbs_v1_0_2_reg__parameterized69 | 4| +|199 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_295 | 4| +|200 | reg_88f |xsdbs_v1_0_2_reg__parameterized71 | 35| +|201 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_294 | 35| +|202 | reg_892 |xsdbs_v1_0_2_reg__parameterized70 | 4| +|203 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_293 | 4| +|204 | reg_9 |xsdbs_v1_0_2_reg__parameterized42 | 14| +|205 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_292 | 14| +|206 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized56 | 93| +|207 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream__parameterized1 | 17| +|208 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 17| +|209 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized2 | 16| +|210 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 16| +|211 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 47| +|212 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|213 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|214 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_288 | 7| +|215 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_289 | 7| +|216 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_290 | 6| +|217 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_291 | 6| +|218 | u_trig |ila_v6_2_9_ila_trigger | 1211| +|219 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 19| +|220 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_283 | 18| +|221 | DUT |ltlib_v1_0_0_all_typeA_284 | 18| +|222 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_285 | 5| +|223 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_286 | 5| +|224 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_287 | 6| +|225 | \N_DDR_TC.N_DDR_TC_INST[10].U_TC |ltlib_v1_0_0_match_0 | 19| +|226 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_278 | 18| +|227 | DUT |ltlib_v1_0_0_all_typeA_279 | 18| +|228 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_280 | 5| +|229 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_281 | 5| +|230 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_282 | 6| +|231 | \N_DDR_TC.N_DDR_TC_INST[11].U_TC |ltlib_v1_0_0_match_1 | 19| +|232 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_273 | 18| +|233 | DUT |ltlib_v1_0_0_all_typeA_274 | 18| +|234 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_275 | 5| +|235 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_276 | 5| +|236 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_277 | 6| +|237 | \N_DDR_TC.N_DDR_TC_INST[12].U_TC |ltlib_v1_0_0_match_2 | 19| +|238 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_268 | 18| +|239 | DUT |ltlib_v1_0_0_all_typeA_269 | 18| +|240 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_270 | 5| +|241 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_271 | 5| +|242 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_272 | 6| +|243 | \N_DDR_TC.N_DDR_TC_INST[13].U_TC |ltlib_v1_0_0_match_3 | 19| +|244 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_263 | 18| +|245 | DUT |ltlib_v1_0_0_all_typeA_264 | 18| +|246 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_265 | 5| +|247 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_266 | 5| +|248 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_267 | 6| +|249 | \N_DDR_TC.N_DDR_TC_INST[14].U_TC |ltlib_v1_0_0_match_4 | 19| +|250 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_258 | 18| +|251 | DUT |ltlib_v1_0_0_all_typeA_259 | 18| +|252 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_260 | 5| +|253 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_261 | 5| +|254 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_262 | 6| +|255 | \N_DDR_TC.N_DDR_TC_INST[15].U_TC |ltlib_v1_0_0_match_5 | 19| +|256 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_253 | 18| +|257 | DUT |ltlib_v1_0_0_all_typeA_254 | 18| +|258 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_255 | 5| +|259 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_256 | 5| +|260 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_257 | 6| +|261 | \N_DDR_TC.N_DDR_TC_INST[16].U_TC |ltlib_v1_0_0_match_6 | 19| +|262 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_248 | 18| +|263 | DUT |ltlib_v1_0_0_all_typeA_249 | 18| +|264 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_250 | 5| +|265 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_251 | 5| +|266 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_252 | 6| +|267 | \N_DDR_TC.N_DDR_TC_INST[17].U_TC |ltlib_v1_0_0_match_7 | 19| +|268 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_243 | 18| +|269 | DUT |ltlib_v1_0_0_all_typeA_244 | 18| +|270 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_245 | 5| +|271 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_246 | 5| +|272 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_247 | 6| +|273 | \N_DDR_TC.N_DDR_TC_INST[18].U_TC |ltlib_v1_0_0_match_8 | 19| +|274 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_238 | 18| +|275 | DUT |ltlib_v1_0_0_all_typeA_239 | 18| +|276 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_240 | 5| +|277 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_241 | 5| +|278 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_242 | 6| +|279 | \N_DDR_TC.N_DDR_TC_INST[19].U_TC |ltlib_v1_0_0_match_9 | 19| +|280 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_233 | 18| +|281 | DUT |ltlib_v1_0_0_all_typeA_234 | 18| +|282 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_235 | 5| +|283 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_236 | 5| +|284 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_237 | 6| +|285 | \N_DDR_TC.N_DDR_TC_INST[1].U_TC |ltlib_v1_0_0_match_10 | 19| +|286 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_228 | 18| +|287 | DUT |ltlib_v1_0_0_all_typeA_229 | 18| +|288 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_230 | 5| +|289 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_231 | 5| +|290 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_232 | 6| +|291 | \N_DDR_TC.N_DDR_TC_INST[20].U_TC |ltlib_v1_0_0_match_11 | 19| +|292 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_223 | 18| +|293 | DUT |ltlib_v1_0_0_all_typeA_224 | 18| +|294 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_225 | 5| +|295 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_226 | 5| +|296 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_227 | 6| +|297 | \N_DDR_TC.N_DDR_TC_INST[21].U_TC |ltlib_v1_0_0_match_12 | 19| +|298 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_218 | 18| +|299 | DUT |ltlib_v1_0_0_all_typeA_219 | 18| +|300 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_220 | 5| +|301 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_221 | 5| +|302 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_222 | 6| +|303 | \N_DDR_TC.N_DDR_TC_INST[22].U_TC |ltlib_v1_0_0_match_13 | 19| +|304 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_213 | 18| +|305 | DUT |ltlib_v1_0_0_all_typeA_214 | 18| +|306 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_215 | 5| +|307 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_216 | 5| +|308 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_217 | 6| +|309 | \N_DDR_TC.N_DDR_TC_INST[23].U_TC |ltlib_v1_0_0_match_14 | 19| +|310 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_208 | 18| +|311 | DUT |ltlib_v1_0_0_all_typeA_209 | 18| +|312 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_210 | 5| +|313 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_211 | 5| +|314 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_212 | 6| +|315 | \N_DDR_TC.N_DDR_TC_INST[24].U_TC |ltlib_v1_0_0_match_15 | 19| +|316 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_203 | 18| +|317 | DUT |ltlib_v1_0_0_all_typeA_204 | 18| +|318 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_205 | 5| +|319 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_206 | 5| +|320 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_207 | 6| +|321 | \N_DDR_TC.N_DDR_TC_INST[25].U_TC |ltlib_v1_0_0_match_16 | 19| +|322 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_198 | 18| +|323 | DUT |ltlib_v1_0_0_all_typeA_199 | 18| +|324 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_200 | 5| +|325 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_201 | 5| +|326 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_202 | 6| +|327 | \N_DDR_TC.N_DDR_TC_INST[26].U_TC |ltlib_v1_0_0_match_17 | 19| +|328 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_193 | 18| +|329 | DUT |ltlib_v1_0_0_all_typeA_194 | 18| +|330 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_195 | 5| +|331 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_196 | 5| +|332 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_197 | 6| +|333 | \N_DDR_TC.N_DDR_TC_INST[27].U_TC |ltlib_v1_0_0_match_18 | 19| +|334 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_188 | 18| +|335 | DUT |ltlib_v1_0_0_all_typeA_189 | 18| +|336 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_190 | 5| +|337 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_191 | 5| +|338 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_192 | 6| +|339 | \N_DDR_TC.N_DDR_TC_INST[28].U_TC |ltlib_v1_0_0_match_19 | 19| +|340 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_183 | 18| +|341 | DUT |ltlib_v1_0_0_all_typeA_184 | 18| +|342 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_185 | 5| +|343 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_186 | 5| +|344 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_187 | 6| +|345 | \N_DDR_TC.N_DDR_TC_INST[29].U_TC |ltlib_v1_0_0_match_20 | 19| +|346 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_178 | 18| +|347 | DUT |ltlib_v1_0_0_all_typeA_179 | 18| +|348 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_180 | 5| +|349 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_181 | 5| +|350 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_182 | 6| +|351 | \N_DDR_TC.N_DDR_TC_INST[2].U_TC |ltlib_v1_0_0_match_21 | 19| +|352 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_173 | 18| +|353 | DUT |ltlib_v1_0_0_all_typeA_174 | 18| +|354 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_175 | 5| +|355 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_176 | 5| +|356 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_177 | 6| +|357 | \N_DDR_TC.N_DDR_TC_INST[30].U_TC |ltlib_v1_0_0_match_22 | 19| +|358 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_168 | 18| +|359 | DUT |ltlib_v1_0_0_all_typeA_169 | 18| +|360 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_170 | 5| +|361 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_171 | 5| +|362 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_172 | 6| +|363 | \N_DDR_TC.N_DDR_TC_INST[31].U_TC |ltlib_v1_0_0_match_23 | 19| +|364 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_163 | 18| +|365 | DUT |ltlib_v1_0_0_all_typeA_164 | 18| +|366 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_165 | 5| +|367 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_166 | 5| +|368 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_167 | 6| +|369 | \N_DDR_TC.N_DDR_TC_INST[3].U_TC |ltlib_v1_0_0_match_24 | 19| +|370 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_158 | 18| +|371 | DUT |ltlib_v1_0_0_all_typeA_159 | 18| +|372 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_160 | 5| +|373 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_161 | 5| +|374 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_162 | 6| +|375 | \N_DDR_TC.N_DDR_TC_INST[4].U_TC |ltlib_v1_0_0_match_25 | 19| +|376 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_153 | 18| +|377 | DUT |ltlib_v1_0_0_all_typeA_154 | 18| +|378 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_155 | 5| +|379 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_156 | 5| +|380 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_157 | 6| +|381 | \N_DDR_TC.N_DDR_TC_INST[5].U_TC |ltlib_v1_0_0_match_26 | 19| +|382 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_148 | 18| +|383 | DUT |ltlib_v1_0_0_all_typeA_149 | 18| +|384 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_150 | 5| +|385 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_151 | 5| +|386 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_152 | 6| +|387 | \N_DDR_TC.N_DDR_TC_INST[6].U_TC |ltlib_v1_0_0_match_27 | 19| +|388 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_143 | 18| +|389 | DUT |ltlib_v1_0_0_all_typeA_144 | 18| +|390 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_145 | 5| +|391 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_146 | 5| +|392 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_147 | 6| +|393 | \N_DDR_TC.N_DDR_TC_INST[7].U_TC |ltlib_v1_0_0_match_28 | 19| +|394 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_138 | 18| +|395 | DUT |ltlib_v1_0_0_all_typeA_139 | 18| +|396 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_140 | 5| +|397 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_141 | 5| +|398 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_142 | 6| +|399 | \N_DDR_TC.N_DDR_TC_INST[8].U_TC |ltlib_v1_0_0_match_29 | 19| +|400 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_133 | 18| +|401 | DUT |ltlib_v1_0_0_all_typeA_134 | 18| +|402 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_135 | 5| +|403 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_136 | 5| +|404 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_137 | 6| +|405 | \N_DDR_TC.N_DDR_TC_INST[9].U_TC |ltlib_v1_0_0_match_30 | 19| +|406 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_128 | 18| +|407 | DUT |ltlib_v1_0_0_all_typeA_129 | 18| +|408 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_130 | 5| +|409 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_131 | 5| +|410 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_132 | 6| +|411 | \STRG_QUAL.U_STRG_QUAL |ltlib_v1_0_0_match_31 | 39| +|412 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 38| +|413 | DUT |ltlib_v1_0_0_all_typeA | 18| +|414 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_125 | 5| +|415 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_126 | 5| +|416 | \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_127 | 6| +|417 | U_TM |ila_v6_2_9_ila_trig_match | 516| +|418 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| +|419 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_121 | 37| +|420 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_122 | 13| +|421 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_123 | 5| +|422 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_124 | 6| +|423 | \N_DDR_MODE.G_NMU[10].U_M |ltlib_v1_0_0_match__parameterized0_32 | 38| +|424 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_117 | 37| +|425 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_118 | 13| +|426 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_119 | 5| +|427 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_120 | 6| +|428 | \N_DDR_MODE.G_NMU[11].U_M |ltlib_v1_0_0_match__parameterized0_33 | 14| +|429 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_113 | 13| +|430 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_114 | 13| +|431 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_115 | 5| +|432 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_116 | 6| +|433 | \N_DDR_MODE.G_NMU[12].U_M |ltlib_v1_0_0_match__parameterized0_34 | 38| +|434 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_109 | 37| +|435 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_110 | 13| +|436 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_111 | 5| +|437 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_112 | 6| +|438 | \N_DDR_MODE.G_NMU[13].U_M |ltlib_v1_0_0_match__parameterized0_35 | 14| +|439 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_105 | 13| +|440 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_106 | 13| +|441 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_107 | 5| +|442 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_108 | 6| +|443 | \N_DDR_MODE.G_NMU[14].U_M |ltlib_v1_0_0_match__parameterized0_36 | 38| +|444 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_101 | 37| +|445 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_102 | 13| +|446 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_103 | 5| +|447 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_104 | 6| +|448 | \N_DDR_MODE.G_NMU[15].U_M |ltlib_v1_0_0_match__parameterized0_37 | 14| +|449 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_97 | 13| +|450 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_98 | 13| +|451 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_99 | 5| +|452 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_100 | 6| +|453 | \N_DDR_MODE.G_NMU[16].U_M |ltlib_v1_0_0_match__parameterized0_38 | 38| +|454 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_93 | 37| +|455 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_94 | 13| +|456 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_95 | 5| +|457 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_96 | 6| +|458 | \N_DDR_MODE.G_NMU[17].U_M |ltlib_v1_0_0_match__parameterized0_39 | 14| +|459 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_89 | 13| +|460 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_90 | 13| +|461 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_91 | 5| +|462 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_92 | 6| +|463 | \N_DDR_MODE.G_NMU[18].U_M |ltlib_v1_0_0_match__parameterized1 | 34| +|464 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_85 | 33| +|465 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_86 | 13| +|466 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_87 | 5| +|467 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_88 | 6| +|468 | \N_DDR_MODE.G_NMU[19].U_M |ltlib_v1_0_0_match__parameterized1_40 | 14| +|469 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 13| +|470 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_82 | 13| +|471 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_83 | 5| +|472 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_84 | 6| +|473 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized0_41 | 14| +|474 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_78 | 13| +|475 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_79 | 13| +|476 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_80 | 5| +|477 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_81 | 6| +|478 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized0_42 | 38| +|479 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_74 | 37| +|480 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_75 | 13| +|481 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_76 | 5| +|482 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_77 | 6| +|483 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized0_43 | 14| +|484 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_70 | 13| +|485 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_71 | 13| +|486 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_72 | 5| +|487 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_73 | 6| +|488 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized0_44 | 38| +|489 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_66 | 37| +|490 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_67 | 13| +|491 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_68 | 5| +|492 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_69 | 6| +|493 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized0_45 | 14| +|494 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_62 | 13| +|495 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_63 | 13| +|496 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_64 | 5| +|497 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_65 | 6| +|498 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized0_46 | 38| +|499 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_58 | 37| +|500 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_59 | 13| +|501 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_60 | 5| +|502 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_61 | 6| +|503 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized0_47 | 14| +|504 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_54 | 13| +|505 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_55 | 13| +|506 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_56 | 5| +|507 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_57 | 6| +|508 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized0_48 | 38| +|509 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_50 | 37| +|510 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_51 | 13| +|511 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_52 | 5| +|512 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_53 | 6| +|513 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_49 | 14| +|514 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 13| +|515 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 13| +|516 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|517 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|518 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 238| ++------+------------------------------------------------------------------------+-------------------------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 429 ; free virtual = 52156 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1142 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:55 ; elapsed = 00:01:07 . Memory (MB): peak = 2356.613 ; gain = 538.414 ; free physical = 476 ; free virtual = 52203 +Synthesis Optimization Complete : Time (s): cpu = 00:00:58 ; elapsed = 00:01:10 . Memory (MB): peak = 2356.613 ; gain = 635.258 ; free physical = 496 ; free virtual = 52223 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1060 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.613 ; gain = 0.000 ; free physical = 454 ; free virtual = 52136 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 668 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 580 instances + CFGLUT5 => SRLC32E: 56 instances + RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +348 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:02 ; elapsed = 00:01:14 . Memory (MB): peak = 2356.613 ; gain = 945.160 ; free physical = 550 ; free virtual = 52233 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.613 ; gain = 0.000 ; free physical = 550 ; free virtual = 52233 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rx_data_cnt, cache-ID = b21318091042a7f7 +INFO: [Coretcl 2-1174] Renamed 517 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2380.625 ; gain = 0.000 ; free physical = 543 ; free virtual = 52147 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed May 10 18:23:01 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v new file mode 100644 index 00000000..a4adeba4 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c06d768c3fffa219f88e077f580f26ef5604b6a1f307543b6e430d4db7dcdfc6 +size 4423015 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl new file mode 100644 index 00000000..ece33838 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3d7ea2a94adf194396a25c01706e4c33015f8e1f88b084b194c7d0f65cb791df +size 6609619 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v new file mode 100644 index 00000000..382c80fb --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Wed May 10 18:23:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v +// Design : ila_rx_data_cnt +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]" */; + input clk; + input [11:0]probe0; + input [11:0]probe1; + input [11:0]probe2; + input [11:0]probe3; + input [11:0]probe4; + input [11:0]probe5; + input [11:0]probe6; + input [11:0]probe7; + input [11:0]probe8; + input [9:0]probe9; +endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl new file mode 100644 index 00000000..d7728a4f --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Wed May 10 18:23:01 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl +-- Design : ila_rx_data_cnt +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rx_data_cnt is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe9 : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + +end ila_rx_data_cnt; + +architecture stub of ila_rx_data_cnt is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb new file mode 100644 index 00000000..9f2b81b8 Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt new file mode 100644 index 00000000..0714aaec --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_utilization_synth.rpt @@ -0,0 +1,194 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Wed May 10 18:23:01 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file ila_rx_data_cnt_utilization_synth.rpt -pb ila_rx_data_cnt_utilization_synth.pb +| Design : ila_rx_data_cnt +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 3586 | 0 | 277400 | 1.29 | +| LUT as Logic | 2677 | 0 | 277400 | 0.97 | +| LUT as Memory | 909 | 0 | 108200 | 0.84 | +| LUT as Distributed RAM | 128 | 0 | | | +| LUT as Shift Register | 781 | 0 | | | +| Slice Registers | 4428 | 0 | 554800 | 0.80 | +| Register as Flip Flop | 4428 | 0 | 554800 | 0.80 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 135 | 0 | 138700 | 0.10 | +| F8 Muxes | 2 | 0 | 69350 | <0.01 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 9 | Yes | Set | - | +| 4419 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 26.5 | 0 | 755 | 3.51 | +| RAMB36/FIFO* | 26 | 0 | 755 | 3.44 | +| RAMB36E1 only | 26 | | | | +| RAMB18 | 1 | 0 | 1510 | 0.07 | +| RAMB18E1 only | 1 | | | | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 4419 | Flop & Latch | +| LUT6 | 1602 | LUT | +| SRL16E | 706 | Distributed Memory | +| SRLC32E | 653 | Distributed Memory | +| LUT4 | 558 | LUT | +| LUT3 | 378 | LUT | +| LUT5 | 254 | LUT | +| CARRY4 | 228 | CarryLogic | +| MUXF7 | 135 | MuxFx | +| RAMD64E | 128 | Distributed Memory | +| LUT2 | 111 | LUT | +| LUT1 | 90 | LUT | +| RAMB36E1 | 26 | Block Memory | +| FDSE | 9 | Flop & Latch | +| SRLC16E | 2 | Distributed Memory | +| MUXF8 | 2 | MuxFx | +| RAMB18E1 | 1 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf new file mode 100644 index 00000000..41f57224 --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/project.wdf @@ -0,0 +1,42 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh new file mode 100755 index 00000000..24de35fa --- /dev/null +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log ila_rx_data_cnt.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rx_data_cnt.tcl diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb new file mode 100644 index 00000000..15f32e6b Binary files /dev/null and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml index 12202685..73fbdf14 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml index b1fba6e9..4d69326a 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml @@ -1,9 +1,9 @@ - - + + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst index 55aa00b2..1050006e 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml index da8950f1..642d1253 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/gen_run.xml @@ -1,20 +1,23 @@ - - - - + + + - + + + + + - + - + @@ -27,14 +30,14 @@ - + - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf index c1ef2fc1..3a1d0ffa 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/project.wdf @@ -6,17 +6,18 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:39:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:39:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3130:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657034:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f646174615f636e74:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6d756c745f67656e5f7631325f305f31355c6d756c745f3138783138:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f667265715f776f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00 @@ -30,12 +31,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3236:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3236:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 -eof:3099610940 +eof:2413169339 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh index 2bff452c..352154db 100755 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/runme.sh @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1' +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp index 0ed17db4..821c3b5f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c220c5a859a43924996f76569432e04e0649230e0f3869f1979d1665fb4dd5b9 -size 142892 +oid sha256:2782003cc5a337831903b3b576dbd3fdb199accf0747ec7bae08b550cb1652ae +size 146765 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl index cb130ecf..0a6f2068 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.tcl @@ -27,16 +27,16 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -48,7 +48,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 -new_name vio_freq_comp -ip [get_ips vio_freq_comp]] +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 -new_name vio_freq_comp -ip [get_ips vio_freq_comp]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -89,25 +89,25 @@ write_checkpoint -force -noxdef vio_freq_comp.dcp create_report "vio_freq_comp_synth_1_synth_report_utilization_0" "report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -118,37 +118,37 @@ if { [catch { }; # end if cached_ip -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci] -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_freq_comp + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp } } file delete __synthesis_is_running__ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds index 0a2f9e10..100ebedb 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds @@ -2,12 +2,12 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 13:15:05 2023 -# Process ID: 2006878 -# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 +# Start of session at: Wed May 10 18:22:57 2023 +# Process ID: 229359 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1 # Command line: vivado -log vio_freq_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_freq_comp.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.jou +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.jou #----------------------------------------------------------- source vio_freq_comp.tcl -notrace Command: synth_design -top vio_freq_comp -part xc7z100ffg900-2 -mode out_of_context @@ -16,14 +16,13 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Device 21-403] Loading part xc7z100ffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2007149 +INFO: Helper process launched with PID 229678 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1858.629 ; gain = 152.719 ; free physical = 861 ; free virtual = 39827 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.441 ; gain = 150.688 ; free physical = 805 ; free virtual = 52417 --------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_freq_comp' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:78] -INFO: [Synth 8-6155] done synthesizing module 'vio_freq_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/synth/vio_freq_comp.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +INFO: [Synth 8-6157] synthesizing module 'vio_freq_comp' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/synth/vio_freq_comp.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_freq_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/synth/vio_freq_comp.v:80] +INFO: [Synth 8-6155] done synthesizing module 'vio_freq_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/synth/vio_freq_comp.v:59] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] @@ -42,6 +41,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bu WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] @@ -125,7 +125,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in68[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in69[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1921.316 ; gain = 215.406 ; free physical = 880 ; free virtual = 39551 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.160 ; gain = 212.406 ; free physical = 809 ; free virtual = 52436 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,44 +138,44 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1924.285 ; gain = 218.375 ; free physical = 839 ; free virtual = 39475 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1928.098 ; gain = 218.344 ; free physical = 808 ; free virtual = 52438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1924.285 ; gain = 218.375 ; free physical = 839 ; free virtual = 39475 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1928.098 ; gain = 218.344 ; free physical = 808 ; free virtual = 52438 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_freq_comp/vio_freq_comp.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2096.973 ; gain = 0.000 ; free physical = 914 ; free virtual = 39183 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2099.754 ; gain = 0.000 ; free physical = 666 ; free virtual = 52310 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2103.910 ; gain = 6.938 ; free physical = 910 ; free virtual = 39179 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2105.691 ; gain = 5.938 ; free physical = 664 ; free virtual = 52309 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1087 ; free virtual = 39333 +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 634 ; free virtual = 52302 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z100ffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1087 ; free virtual = 39333 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 634 ; free virtual = 52302 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1082 ; free virtual = 39328 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 633 ; free virtual = 52301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1065 ; free virtual = 39315 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 583 ; free virtual = 52255 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -188,22 +188,22 @@ Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 2 Bit Adders := 1 - 2 Input 1 Bit Adders := 1 + 2 Input 2 Bit Adders := 2 +---Registers : 128 Bit Registers := 1 32 Bit Registers := 1 16 Bit Registers := 13 + 13 Bit Registers := 1 8 Bit Registers := 1 7 Bit Registers := 1 5 Bit Registers := 1 - 3 Bit Registers := 2 + 3 Bit Registers := 3 2 Bit Registers := 2 - 1 Bit Registers := 25 + 1 Bit Registers := 26 +---Muxes : 2 Input 16 Bit Muxes := 3 - 4 Input 16 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 10 + 3 Input 13 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 11 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -245,18 +245,19 @@ Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 2 Bit Registers := 1 - 1 Bit Registers := 6 + 3 Bit Registers := 1 + 1 Bit Registers := 7 +---Muxes : - 4 Input 16 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module vio_v3_0_20_probe_width Detailed RTL Component Info : +---Adders : - 2 Input 1 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 +---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 + 13 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 13 Bit Muxes := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -297,63 +298,72 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' -INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] ) -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' (FDS) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[13]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 1022 ; free virtual = 39277 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 571 ; free virtual = 52253 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -365,13 +375,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 925 ; free virtual = 38886 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 471 ; free virtual = 52182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 924 ; free virtual = 38885 +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 470 ; free virtual = 52181 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -383,7 +393,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 922 ; free virtual = 38872 +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 462 ; free virtual = 52176 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -444,7 +454,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 925 ; free virtual = 38742 +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 458 ; free virtual = 52175 --------------------------------------------------------------------------------- Report Check Netlist: @@ -457,7 +467,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 924 ; free virtual = 38740 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 458 ; free virtual = 52175 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -469,25 +479,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 913 ; free virtual = 38729 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 457 ; free virtual = 52175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 911 ; free virtual = 38728 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 457 ; free virtual = 52175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 915 ; free virtual = 38732 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 457 ; free virtual = 52175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 915 ; free virtual = 38731 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 457 ; free virtual = 52175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -503,13 +513,13 @@ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ -|1 |LUT1 | 1| -|2 |LUT2 | 8| -|3 |LUT3 | 51| +|1 |LUT1 | 2| +|2 |LUT2 | 9| +|3 |LUT3 | 61| |4 |LUT4 | 11| -|5 |LUT5 | 13| -|6 |LUT6 | 84| -|7 |FDRE | 355| +|5 |LUT5 | 19| +|6 |LUT6 | 82| +|7 |FDRE | 360| |8 |FDSE | 4| +------+-----+------+ @@ -517,45 +527,46 @@ Report Instance Areas: +------+---------------------------------------+------------------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------+------------------------------------------+------+ -|1 |top | | 527| -|2 | inst |vio_v3_0_20_vio | 527| +|1 |top | | 548| +|2 | inst |vio_v3_0_20_vio | 548| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 80| +|4 | DECODER_INST |vio_v3_0_20_decoder | 79| |5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 18| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 163| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 179| |7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| |8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 16| |9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| |10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 105| -|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 2| +|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|12 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 8| +------+---------------------------------------+------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 914 ; free virtual = 38731 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 457 ; free virtual = 52175 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2103.910 ; gain = 218.375 ; free physical = 947 ; free virtual = 38763 -Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2103.910 ; gain = 398.000 ; free physical = 947 ; free virtual = 38763 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2105.691 ; gain = 218.344 ; free physical = 509 ; free virtual = 52231 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.691 ; gain = 395.938 ; free physical = 513 ; free virtual = 52235 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.910 ; gain = 0.000 ; free physical = 900 ; free virtual = 38616 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.691 ; gain = 0.000 ; free physical = 448 ; free virtual = 52176 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -67 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +76 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2103.910 ; gain = 706.934 ; free physical = 991 ; free virtual = 38707 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.910 ; gain = 0.000 ; free physical = 991 ; free virtual = 38707 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2105.691 ; gain = 706.777 ; free physical = 546 ; free virtual = 52274 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.691 ; gain = 0.000 ; free physical = 546 ; free virtual = 52274 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_freq_comp, cache-ID = 93753bc8666fbd09 -INFO: [Coretcl 2-1174] Renamed 10 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2127.922 ; gain = 0.000 ; free physical = 957 ; free virtual = 38646 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_freq_comp, cache-ID = 67483215c55000dc +INFO: [Coretcl 2-1174] Renamed 11 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2129.703 ; gain = 0.000 ; free physical = 542 ; free virtual = 52276 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:25 2023... +INFO: [Common 17-206] Exiting Vivado at Wed May 10 18:23:14 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v index daabb4af..ee0fa2ec 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c34539843f7fa4c5906209eef95783110cbf58f52a239344578ff4d3cfabfab3 -size 347789 +oid sha256:194adcb2584460a0c49f443e10ff808afc50b94c08121d3b2a8799894a5cd8f0 +size 356709 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl index ced3f879..8ba3790d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:ab1d7e314e1d93fce13386e493892ccc6fd24d37980345a48e6d890ba0520334 -size 625987 +oid sha256:284e403615e7267061792d90faf87676725b1d0f13edce936f4f9ad73d9189dd +size 636069 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v index 85124391..4f7d1942 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 13:15:24 2023 +// Date : Wed May 10 18:23:14 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v // Design : vio_freq_comp // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -15,12 +15,13 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */; + probe_out2, probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]" */; input clk; input [0:0]probe_in0; output [0:0]probe_out0; output [7:0]probe_out1; output [0:0]probe_out2; output [31:0]probe_out3; + output [0:0]probe_out4; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl index 015c276d..c08c2d99 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 13:15:24 2023 +-- Date : Wed May 10 18:23:14 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl -- Design : vio_freq_comp -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -19,7 +19,8 @@ entity vio_freq_comp is probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_freq_comp; @@ -28,7 +29,7 @@ architecture stub of vio_freq_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb index 990c3d13..974b1af4 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt index 18e76da6..5894b5db 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 13:15:24 2023 +| Date : Wed May 10 18:23:14 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_freq_comp_utilization_synth.rpt -pb vio_freq_comp_utilization_synth.pb | Design : vio_freq_comp @@ -30,11 +30,11 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 141 | 0 | 277400 | 0.05 | -| LUT as Logic | 141 | 0 | 277400 | 0.05 | +| Slice LUTs* | 146 | 0 | 277400 | 0.05 | +| LUT as Logic | 146 | 0 | 277400 | 0.05 | | LUT as Memory | 0 | 0 | 108200 | 0.00 | -| Slice Registers | 359 | 0 | 554800 | 0.06 | -| Register as Flip Flop | 359 | 0 | 554800 | 0.06 | +| Slice Registers | 364 | 0 | 554800 | 0.07 | +| Register as Flip Flop | 364 | 0 | 554800 | 0.07 | | Register as Latch | 0 | 0 | 554800 | 0.00 | | F7 Muxes | 0 | 0 | 138700 | 0.00 | | F8 Muxes | 0 | 0 | 69350 | 0.00 | @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 4 | Yes | Set | - | -| 355 | Yes | Reset | - | +| 360 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,14 +152,14 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 355 | Flop & Latch | -| LUT6 | 84 | LUT | -| LUT3 | 51 | LUT | -| LUT5 | 13 | LUT | +| FDRE | 360 | Flop & Latch | +| LUT6 | 82 | LUT | +| LUT3 | 61 | LUT | +| LUT5 | 19 | LUT | | LUT4 | 11 | LUT | -| LUT2 | 8 | LUT | +| LUT2 | 9 | LUT | | FDSE | 4 | Flop & Latch | -| LUT1 | 1 | LUT | +| LUT1 | 2 | LUT | +----------+------+---------------------+ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb index a8c04925..fbe0ab77 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml index 4769398c..856dc101 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst index 74165460..bd8edadc 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index 34fcadaf..d5c748a0 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,20 +1,23 @@ - - - - + + + - + + + + + - + - + @@ -27,14 +30,14 @@ - + - + diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf index c1ef2fc1..b9adef6b 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/project.wdf @@ -14,7 +14,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657034:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6d756c745f67656e5f7631325f305f31355c6d756c745f3138783138:636f72655f636f6e7461696e6572:74727565:00:00 @@ -30,12 +30,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3130:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3234:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532646539326639313163333436323238633137626532643735356661343463:506172656e742050412070726f6a656374204944:00 -eof:3099610940 +eof:4073482613 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh index 2b522c2c..445ac0cb 100755 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/runme.sh @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1' +HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp index 7c995c6a..e0782797 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:7cf3a067fc1987bfdb0f1cd0e107ad1450aa77b58b99f773f450abd6cf8384c5 -size 190431 +oid sha256:dc7b6b6970c034204853053c6bb970bd5c4f290b48b0a8c1c512bab69a35ba32 +size 232493 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl index e5b22796..18310944 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.tcl @@ -27,16 +27,16 @@ set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -48,7 +48,7 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { } set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 -new_name vio_rfcontrl -ip [get_ips vio_rfcontrl]] +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 -new_name vio_rfcontrl -ip [get_ips vio_rfcontrl]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] @@ -89,25 +89,25 @@ write_checkpoint -force -noxdef vio_rfcontrl.dcp create_report "vio_rfcontrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -118,37 +118,37 @@ if { [catch { }; # end if cached_ip -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci] -add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci] +add_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xci] -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/ip_user_files/ip/vio_rfcontrl + file copy -force /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_rfcontrl } } file delete __synthesis_is_running__ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds index 7494f5e9..f48577c5 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds @@ -2,12 +2,12 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Mon May 8 13:15:05 2023 -# Process ID: 2006880 -# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 +# Start of session at: Wed May 10 18:19:54 2023 +# Process ID: 226858 +# Current directory: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1 # Command line: vivado -log vio_rfcontrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rfcontrl.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.jou +# Log file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.jou #----------------------------------------------------------- source vio_rfcontrl.tcl -notrace Command: synth_design -top vio_rfcontrl -part xc7z100ffg900-2 -mode out_of_context @@ -16,13 +16,14 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' INFO: [Device 21-403] Loading part xc7z100ffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 2007378 +INFO: Helper process launched with PID 227155 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.441 ; gain = 150.688 ; free physical = 824 ; free virtual = 39534 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.473 ; gain = 153.688 ; free physical = 451 ; free virtual = 52641 --------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:106] -INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] +INFO: [Synth 8-6157] synthesizing module 'vio_rfcontrl' [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rfcontrl does not have driver. [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/synth/vio_rfcontrl.v:113] +INFO: [Synth 8-6155] done synthesizing module 'vio_rfcontrl' (8#1) [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/synth/vio_rfcontrl.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized6 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Internal_cnt_rst @@ -87,8 +88,6 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unc WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] @@ -123,9 +122,10 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.129 ; gain = 212.375 ; free physical = 917 ; free virtual = 39432 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.191 ; gain = 215.406 ; free physical = 516 ; free virtual = 52656 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,44 +138,44 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.098 ; gain = 216.344 ; free physical = 974 ; free virtual = 39409 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.160 ; gain = 218.375 ; free physical = 524 ; free virtual = 52666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.098 ; gain = 216.344 ; free physical = 974 ; free virtual = 39409 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.160 ; gain = 218.375 ; free physical = 524 ; free virtual = 52666 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl/vio_rfcontrl.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2109.754 ; gain = 0.000 ; free physical = 961 ; free virtual = 39230 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.848 ; gain = 0.000 ; free physical = 440 ; free virtual = 52564 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2115.691 ; gain = 5.938 ; free physical = 950 ; free virtual = 39219 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2114.785 ; gain = 7.938 ; free physical = 439 ; free virtual = 52564 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1074 ; free virtual = 39321 +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 566 ; free virtual = 52711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z100ffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1075 ; free virtual = 39323 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 566 ; free virtual = 52711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1070 ; free virtual = 39317 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 560 ; free virtual = 52705 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 1007 ; free virtual = 39261 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 524 ; free virtual = 52675 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -189,20 +189,24 @@ Start RTL Component Statistics Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 2 +---Registers : 128 Bit Registers := 1 - 16 Bit Registers := 33 - 12 Bit Registers := 1 + 32 Bit Registers := 2 + 17 Bit Registers := 3 + 16 Bit Registers := 38 + 13 Bit Registers := 1 8 Bit Registers := 3 7 Bit Registers := 1 5 Bit Registers := 2 4 Bit Registers := 5 - 3 Bit Registers := 2 - 1 Bit Registers := 38 + 3 Bit Registers := 3 + 2 Bit Registers := 2 + 1 Bit Registers := 40 +---Muxes : - 2 Input 16 Bit Muxes := 2 - 9 Input 12 Bit Muxes := 1 - 2 Input 1 Bit Muxes := 20 + 2 Input 16 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 19 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -212,11 +216,15 @@ Start RTL Hierarchical Component Statistics Hierarchical RTL Component report Module vio_v3_0_20_probe_in_one Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 +---Registers : - 16 Bit Registers := 4 - 1 Bit Registers := 2 + 17 Bit Registers := 3 + 16 Bit Registers := 1 + 3 Bit Registers := 1 + 1 Bit Registers := 1 +---Muxes : - 2 Input 1 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 1 Module vio_v3_0_20_probe_out_one Detailed RTL Component Info : +---Registers : @@ -257,12 +265,22 @@ Module vio_v3_0_20_probe_out_one__parameterized5 Detailed RTL Component Info : +---Registers : 16 Bit Registers := 2 +Module vio_v3_0_20_probe_out_one__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 5 Bit Registers := 1 - 1 Bit Registers := 20 + 1 Bit Registers := 23 +---Muxes : 2 Input 1 Bit Muxes := 2 Module vio_v3_0_20_probe_width @@ -270,10 +288,8 @@ Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : - 12 Bit Registers := 1 + 13 Bit Registers := 1 4 Bit Registers := 1 -+---Muxes : - 9 Input 12 Bit Muxes := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -430,7 +446,7 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PRO INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 974 ; free virtual = 39241 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 490 ; free virtual = 52661 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -442,13 +458,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 920 ; free virtual = 38697 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 457 ; free virtual = 52576 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 918 ; free virtual = 38695 +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 446 ; free virtual = 52565 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -460,7 +476,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 913 ; free virtual = 38651 +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 439 ; free virtual = 52559 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -521,7 +537,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 928 ; free virtual = 38616 +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52556 --------------------------------------------------------------------------------- Report Check Netlist: @@ -534,7 +550,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 927 ; free virtual = 38616 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52556 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -546,25 +562,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 923 ; free virtual = 38612 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 916 ; free virtual = 38605 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 912 ; free virtual = 38600 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 910 ; free virtual = 38598 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -577,29 +593,31 @@ Report BlackBoxes: +-+--------------+----------+ Report Cell Usage: -+------+-----+------+ -| |Cell |Count | -+------+-----+------+ -|1 |LUT1 | 2| -|2 |LUT2 | 16| -|3 |LUT3 | 35| -|4 |LUT4 | 11| -|5 |LUT5 | 42| -|6 |LUT6 | 122| -|7 |FDRE | 569| -|8 |FDSE | 24| -+------+-----+------+ ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 9| +|3 |LUT3 | 69| +|4 |LUT4 | 28| +|5 |LUT5 | 62| +|6 |LUT6 | 120| +|7 |MUXF7 | 8| +|8 |MUXF8 | 4| +|9 |FDRE | 775| +|10 |FDSE | 24| ++------+------+------+ Report Instance Areas: +------+----------------------------------------+---------------------------------------------+------+ | |Instance |Module |Cells | +------+----------------------------------------+---------------------------------------------+------+ -|1 |top | | 821| -|2 | inst |vio_v3_0_20_vio | 821| +|1 |top | | 1101| +|2 | inst |vio_v3_0_20_vio | 1101| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 91| +|4 | DECODER_INST |vio_v3_0_20_decoder | 101| |5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 77| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 367| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 633| |7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| |8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 32| |9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_0 | 32| @@ -609,44 +627,49 @@ Report Instance Areas: |13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| |14 | \G_PROBE_OUT[16].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_4 | 3| |15 | \G_PROBE_OUT[17].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_5 | 32| -|16 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| -|17 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32| -|18 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| -|19 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8| -|20 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_7 | 8| -|21 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_8 | 8| -|22 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_9 | 8| -|23 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_10 | 16| -|24 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16| -|25 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 22| +|16 | \G_PROBE_OUT[18].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_6 | 32| +|17 | \G_PROBE_OUT[19].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6 | 101| +|18 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3| +|19 | \G_PROBE_OUT[20].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6_8 | 105| +|20 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 32| +|21 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| +|22 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 8| +|23 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_9 | 8| +|24 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_10 | 8| +|25 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2_11 | 8| +|26 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_12 | 16| +|27 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 16| +|28 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 26| +------+----------------------------------------+---------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 910 ; free virtual = 38599 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 431 ; free virtual = 52555 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2115.691 ; gain = 216.344 ; free physical = 959 ; free virtual = 38648 -Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2115.691 ; gain = 405.938 ; free physical = 972 ; free virtual = 38661 +Synthesis finished with 0 errors, 0 critical warnings and 291 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.785 ; gain = 218.375 ; free physical = 482 ; free virtual = 52609 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.785 ; gain = 408.000 ; free physical = 496 ; free virtual = 52622 INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.691 ; gain = 0.000 ; free physical = 954 ; free virtual = 38548 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.785 ; gain = 0.000 ; free physical = 451 ; free virtual = 52485 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -127 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +129 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2115.691 ; gain = 716.777 ; free physical = 1167 ; free virtual = 38760 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.691 ; gain = 0.000 ; free physical = 1168 ; free virtual = 38762 +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2114.785 ; gain = 715.871 ; free physical = 544 ; free virtual = 52578 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.785 ; gain = 0.000 ; free physical = 544 ; free virtual = 52578 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 33802de7d605f892 -INFO: [Coretcl 2-1174] Renamed 24 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2139.703 ; gain = 0.000 ; free physical = 1872 ; free virtual = 39468 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rfcontrl, cache-ID = 3562b3f5445704f9 +INFO: [Coretcl 2-1174] Renamed 27 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2138.797 ; gain = 0.000 ; free physical = 548 ; free virtual = 52592 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Mon May 8 13:15:26 2023... +INFO: [Common 17-206] Exiting Vivado at Wed May 10 18:20:13 2023... diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v index 045f923b..69cd8916 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:795e37fa5092bed76bd5666e05cb723247face647baf3ad8fae43fc62a1b160e -size 429585 +oid sha256:4f1a9f92eb36bfc1a930fea2d1f29f4906f55062c43bfb8ba026dcd0c6c7688e +size 498496 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl index 947c8fdd..be83dab8 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f9b2adcaf809ac070ceed79970f8ed6d58a91149d1358bbad5cf3844870fef4 -size 743518 +oid sha256:c1a367565775776ceb2634eb84be77f5f08c895752497ff1c94169a9551b7a83 +size 836814 diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v index 1d32ada2..b537fe6d 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 13:15:25 2023 +// Date : Wed May 10 18:20:13 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v +// /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v // Design : vio_rfcontrl // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -14,13 +14,14 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, - probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, - probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, - probe_out17) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */; +module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0, + probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, + probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, + probe_out16, probe_out17, probe_out18, probe_out19, probe_out20) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]" */; input clk; input [15:0]probe_in0; + input [0:0]probe_in1; output [0:0]probe_out0; output [0:0]probe_out1; output [15:0]probe_out2; @@ -39,4 +40,7 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, output [0:0]probe_out15; output [0:0]probe_out16; output [15:0]probe_out17; + output [15:0]probe_out18; + output [31:0]probe_out19; + output [31:0]probe_out20; endmodule diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl index ba0a2f31..cf20e31f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 13:15:25 2023 +-- Date : Wed May 10 18:20:13 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl -- Design : vio_rfcontrl -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -16,6 +16,7 @@ entity vio_rfcontrl is Port ( clk : in STD_LOGIC; probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); @@ -33,7 +34,10 @@ entity vio_rfcontrl is probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out18 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end vio_rfcontrl; @@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb index 4a83b4e8..57c2daae 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt index 0edcd8e8..c3d6c13f 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Mon May 8 13:15:25 2023 +| Date : Wed May 10 18:20:13 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_rfcontrl_utilization_synth.rpt -pb vio_rfcontrl_utilization_synth.pb | Design : vio_rfcontrl @@ -30,14 +30,14 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 203 | 0 | 277400 | 0.07 | -| LUT as Logic | 203 | 0 | 277400 | 0.07 | +| Slice LUTs* | 247 | 0 | 277400 | 0.09 | +| LUT as Logic | 247 | 0 | 277400 | 0.09 | | LUT as Memory | 0 | 0 | 108200 | 0.00 | -| Slice Registers | 593 | 0 | 554800 | 0.11 | -| Register as Flip Flop | 593 | 0 | 554800 | 0.11 | +| Slice Registers | 799 | 0 | 554800 | 0.14 | +| Register as Flip Flop | 799 | 0 | 554800 | 0.14 | | Register as Latch | 0 | 0 | 554800 | 0.00 | -| F7 Muxes | 0 | 0 | 138700 | 0.00 | -| F8 Muxes | 0 | 0 | 69350 | 0.00 | +| F7 Muxes | 8 | 0 | 138700 | <0.01 | +| F8 Muxes | 4 | 0 | 69350 | <0.01 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 24 | Yes | Set | - | -| 569 | Yes | Reset | - | +| 775 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,13 +152,15 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 569 | Flop & Latch | -| LUT6 | 122 | LUT | -| LUT5 | 42 | LUT | -| LUT3 | 35 | LUT | +| FDRE | 775 | Flop & Latch | +| LUT6 | 120 | LUT | +| LUT3 | 69 | LUT | +| LUT5 | 62 | LUT | +| LUT4 | 28 | LUT | | FDSE | 24 | Flop & Latch | -| LUT2 | 16 | LUT | -| LUT4 | 11 | LUT | +| LUT2 | 9 | LUT | +| MUXF7 | 8 | MuxFx | +| MUXF8 | 4 | MuxFx | | LUT1 | 2 | LUT | +----------+------+---------------------+ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb index 8b337497..52674dfe 100644 Binary files a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb and b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vivado.pb differ diff --git a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr index c4723e03..0b2203f3 100644 --- a/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@ + + + + + + + + + + + + + + + + + + @@ -391,6 +411,15 @@ + + + + + + + + + Vivado Synthesis Defaults @@ -530,6 +559,22 @@ + + + + + + + + + + + + + + + + Default settings for Implementation. diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix index dbd8f935..0658c845 100644 --- a/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix +++ b/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:71b6e9fe05c8bb3bf625454b16ed66378b2e932a379fbf863749545aa64f9b5d -size 717725 +oid sha256:c9fa28bf087abbed71e63b3389da6db0e13d262cd2151e509c895a795fec0f42 +size 723570 diff --git a/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix b/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix index e693102f..4ea017c7 100644 --- a/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix +++ b/projects/duifei/duifei_online_acq_par/ip/vio_rfcontrl.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a91bb76bc5257de78d7e025f9d9a6605f052fae6df2fe2a5e0e874d1d873e8c -size 780410 +oid sha256:51b4fef214550872042f00fd82c5a703a90b72509d353ed76abd4ddb9f168b3d +size 836073 diff --git a/projects/duifei/duifei_online_acq_par/project.tcl b/projects/duifei/duifei_online_acq_par/project.tcl index 41551623..85c46552 100644 --- a/projects/duifei/duifei_online_acq_par/project.tcl +++ b/projects/duifei/duifei_online_acq_par/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Tue May 09 20:50:10 CST 2023 +# Generated by Vivado on Wed May 10 18:48:33 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -31,7 +31,7 @@ # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_cal/ila_cal.xci" -# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci" +# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci" # "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci" @@ -201,14 +201,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "target_simulator" -value "VCS" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "50" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "50" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "50" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "50" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "50" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "50" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "51" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "51" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "51" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "51" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "51" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "51" -objects $obj set_property -name "webtalk.vcs_launch_sim" -value "47" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "50" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "51" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -230,7 +231,7 @@ set files [list \ [file normalize "${origin_dir}/ip/vio_freq_comp/vio_freq_comp.xci"] \ [file normalize "${origin_dir}/../common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci"] \ [file normalize "${origin_dir}/ip/ila_cal/ila_cal.xci"] \ - [file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci"] \ + [file normalize "${origin_dir}/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci"] \ [file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \ [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"] \ [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \ @@ -330,7 +331,7 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set file "$origin_dir/../common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci" +set file "$origin_dir/ip/ila_rx_data_cnt/ila_rx_data_cnt.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx index 273aff05..d11cff30 100644 --- a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx +++ b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/debug_nets.ltx @@ -2086,7 +2086,7 @@ "portIndex": 13, "nets": [ { - "name": "freq_comp_start_1", + "name": "freq_comp_start", "isBus": false } ] @@ -4572,6 +4572,108 @@ ] } ] + }, + { + "name": "probe8", + "id": 110, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 8, + "nets": [ + { + "name": "vio_frequency__0_2", + "isBus": true, + "subnets": [ + { + "name": "vio_frequency__0_2[11]" + }, + { + "name": "vio_frequency__0_2[10]" + }, + { + "name": "vio_frequency__0_2[9]" + }, + { + "name": "vio_frequency__0_2[8]" + }, + { + "name": "vio_frequency__0_2[7]" + }, + { + "name": "vio_frequency__0_2[6]" + }, + { + "name": "vio_frequency__0_2[5]" + }, + { + "name": "vio_frequency__0_2[4]" + }, + { + "name": "vio_frequency__0_2[3]" + }, + { + "name": "vio_frequency__0_2[2]" + }, + { + "name": "vio_frequency__0_2[1]" + }, + { + "name": "vio_frequency__0_2[0]" + } + ] + } + ] + }, + { + "name": "probe9", + "id": 111, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 9, + "portIndex": 9, + "nets": [ + { + "name": "chip_cnt", + "isBus": true, + "subnets": [ + { + "name": "chip_cnt[9]" + }, + { + "name": "chip_cnt[8]" + }, + { + "name": "chip_cnt[7]" + }, + { + "name": "chip_cnt[6]" + }, + { + "name": "chip_cnt[5]" + }, + { + "name": "chip_cnt[4]" + }, + { + "name": "chip_cnt[3]" + }, + { + "name": "chip_cnt[2]" + }, + { + "name": "chip_cnt[1]" + }, + { + "name": "chip_cnt[0]" + } + ] + } + ] } ] }, @@ -4589,7 +4691,7 @@ "pins": [ { "name": "probe0", - "id": 110, + "id": 112, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -4643,7 +4745,7 @@ }, { "name": "probe1", - "id": 111, + "id": 113, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -4711,7 +4813,7 @@ "pins": [ { "name": "probe_in0", - "id": 112, + "id": 114, "type": "DATA", "direction": "IN", "isVector": true, @@ -4753,7 +4855,7 @@ }, { "name": "probe_in1", - "id": 113, + "id": 115, "type": "DATA", "direction": "IN", "isVector": true, @@ -4795,7 +4897,7 @@ }, { "name": "probe_in2", - "id": 114, + "id": 116, "type": "DATA", "direction": "IN", "isVector": true, @@ -4837,7 +4939,7 @@ }, { "name": "probe_in3", - "id": 115, + "id": 117, "type": "DATA", "direction": "IN", "isVector": true, @@ -4879,7 +4981,7 @@ }, { "name": "probe_in4", - "id": 116, + "id": 118, "type": "DATA", "direction": "IN", "isVector": true, @@ -4993,7 +5095,7 @@ }, { "name": "probe_in5", - "id": 117, + "id": 119, "type": "DATA", "direction": "IN", "isVector": true, @@ -5313,7 +5415,7 @@ "pins": [ { "name": "probe_out0", - "id": 118, + "id": 120, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5329,7 +5431,7 @@ }, { "name": "probe_out1", - "id": 119, + "id": 121, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5345,7 +5447,7 @@ }, { "name": "probe_out2", - "id": 120, + "id": 122, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5361,7 +5463,7 @@ }, { "name": "probe_out3", - "id": 121, + "id": 123, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5441,7 +5543,7 @@ "pins": [ { "name": "probe_in0", - "id": 122, + "id": 124, "type": "DATA", "direction": "IN", "isVector": false, @@ -5457,7 +5559,7 @@ }, { "name": "probe_in1", - "id": 123, + "id": 125, "type": "DATA", "direction": "IN", "isVector": false, @@ -5487,7 +5589,7 @@ "pins": [ { "name": "probe_in0", - "id": 124, + "id": 126, "type": "DATA", "direction": "IN", "isVector": false, @@ -5503,7 +5605,7 @@ }, { "name": "probe_out0", - "id": 125, + "id": 127, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5512,14 +5614,14 @@ "portIndex": 0, "nets": [ { - "name": "freq_comp_start", + "name": "freq_comp_start_vio", "isBus": false } ] }, { "name": "probe_out1", - "id": 126, + "id": 128, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5561,7 +5663,7 @@ }, { "name": "probe_out2", - "id": 127, + "id": 129, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5577,7 +5679,7 @@ }, { "name": "probe_out3", - "id": 128, + "id": 130, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5688,6 +5790,22 @@ ] } ] + }, + { + "name": "probe_out4", + "id": 131, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "freq_comp_auto_enable_vio", + "isBus": false + } + ] } ] }, @@ -5705,7 +5823,7 @@ "pins": [ { "name": "probe_out0", - "id": 129, + "id": 132, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5729,7 +5847,7 @@ }, { "name": "probe_out1", - "id": 130, + "id": 133, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5745,7 +5863,7 @@ }, { "name": "probe_out2", - "id": 131, + "id": 134, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5859,7 +5977,7 @@ }, { "name": "probe_out3", - "id": 132, + "id": 135, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5883,7 +6001,7 @@ }, { "name": "probe_out4", - "id": 133, + "id": 136, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5927,7 +6045,7 @@ "pins": [ { "name": "probe_in0", - "id": 134, + "id": 137, "type": "DATA", "direction": "IN", "isVector": true, @@ -5969,7 +6087,7 @@ }, { "name": "probe_in1", - "id": 135, + "id": 138, "type": "DATA", "direction": "IN", "isVector": true, @@ -6011,7 +6129,7 @@ }, { "name": "probe_in2", - "id": 136, + "id": 139, "type": "DATA", "direction": "IN", "isVector": true, @@ -6053,7 +6171,7 @@ }, { "name": "probe_in3", - "id": 137, + "id": 140, "type": "DATA", "direction": "IN", "isVector": true, @@ -6095,7 +6213,7 @@ }, { "name": "probe_in4", - "id": 138, + "id": 141, "type": "DATA", "direction": "IN", "isVector": true, @@ -6125,7 +6243,7 @@ }, { "name": "probe_in5", - "id": 139, + "id": 142, "type": "DATA", "direction": "IN", "isVector": true, @@ -6155,7 +6273,7 @@ }, { "name": "probe_in6", - "id": 140, + "id": 143, "type": "DATA", "direction": "IN", "isVector": true, @@ -6185,7 +6303,7 @@ }, { "name": "probe_in7", - "id": 141, + "id": 144, "type": "DATA", "direction": "IN", "isVector": true, @@ -6215,7 +6333,7 @@ }, { "name": "probe_in8", - "id": 142, + "id": 145, "type": "DATA", "direction": "IN", "isVector": true, @@ -6329,7 +6447,7 @@ }, { "name": "probe_in9", - "id": 143, + "id": 146, "type": "DATA", "direction": "IN", "isVector": true, @@ -6649,7 +6767,7 @@ "pins": [ { "name": "probe_in0", - "id": 144, + "id": 147, "type": "DATA", "direction": "IN", "isVector": true, @@ -6713,9 +6831,25 @@ } ] }, + { + "name": "probe_in1", + "id": 148, + "type": "DATA", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "debug_io_3_IBUF", + "isBus": false + } + ] + }, { "name": "probe_out0", - "id": 145, + "id": 149, "type": "DATA", "direction": "OUT", "isVector": false, @@ -6731,7 +6865,7 @@ }, { "name": "probe_out1", - "id": 146, + "id": 150, "type": "DATA", "direction": "OUT", "isVector": false, @@ -6747,7 +6881,7 @@ }, { "name": "probe_out2", - "id": 147, + "id": 151, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6813,7 +6947,7 @@ }, { "name": "probe_out3", - "id": 148, + "id": 152, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6855,7 +6989,7 @@ }, { "name": "probe_out4", - "id": 149, + "id": 153, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6885,7 +7019,7 @@ }, { "name": "probe_out5", - "id": 150, + "id": 154, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6915,7 +7049,7 @@ }, { "name": "probe_out6", - "id": 151, + "id": 155, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6945,7 +7079,7 @@ }, { "name": "probe_out7", - "id": 152, + "id": 156, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6975,7 +7109,7 @@ }, { "name": "probe_out8", - "id": 153, + "id": 157, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7017,7 +7151,7 @@ }, { "name": "probe_out9", - "id": 154, + "id": 158, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7059,7 +7193,7 @@ }, { "name": "probe_out10", - "id": 155, + "id": 159, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7125,7 +7259,7 @@ }, { "name": "probe_out11", - "id": 156, + "id": 160, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7191,7 +7325,7 @@ }, { "name": "probe_out12", - "id": 157, + "id": 161, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7257,7 +7391,7 @@ }, { "name": "probe_out13", - "id": 158, + "id": 162, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7273,7 +7407,7 @@ }, { "name": "probe_out14", - "id": 159, + "id": 163, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7289,7 +7423,7 @@ }, { "name": "probe_out15", - "id": 160, + "id": 164, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7305,7 +7439,7 @@ }, { "name": "probe_out16", - "id": 161, + "id": 165, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7321,7 +7455,7 @@ }, { "name": "probe_out17", - "id": 162, + "id": 166, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7384,6 +7518,300 @@ ] } ] + }, + { + "name": "probe_out18", + "id": 167, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 18, + "nets": [ + { + "name": "cnt_switch_to_freq_start_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_switch_to_freq_start_vio[15]" + }, + { + "name": "cnt_switch_to_freq_start_vio[14]" + }, + { + "name": "cnt_switch_to_freq_start_vio[13]" + }, + { + "name": "cnt_switch_to_freq_start_vio[12]" + }, + { + "name": "cnt_switch_to_freq_start_vio[11]" + }, + { + "name": "cnt_switch_to_freq_start_vio[10]" + }, + { + "name": "cnt_switch_to_freq_start_vio[9]" + }, + { + "name": "cnt_switch_to_freq_start_vio[8]" + }, + { + "name": "cnt_switch_to_freq_start_vio[7]" + }, + { + "name": "cnt_switch_to_freq_start_vio[6]" + }, + { + "name": "cnt_switch_to_freq_start_vio[5]" + }, + { + "name": "cnt_switch_to_freq_start_vio[4]" + }, + { + "name": "cnt_switch_to_freq_start_vio[3]" + }, + { + "name": "cnt_switch_to_freq_start_vio[2]" + }, + { + "name": "cnt_switch_to_freq_start_vio[1]" + }, + { + "name": "cnt_switch_to_freq_start_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out19", + "id": 168, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 19, + "nets": [ + { + "name": "cnt_sync_in_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_sync_in_vio[31]" + }, + { + "name": "cnt_sync_in_vio[30]" + }, + { + "name": "cnt_sync_in_vio[29]" + }, + { + "name": "cnt_sync_in_vio[28]" + }, + { + "name": "cnt_sync_in_vio[27]" + }, + { + "name": "cnt_sync_in_vio[26]" + }, + { + "name": "cnt_sync_in_vio[25]" + }, + { + "name": "cnt_sync_in_vio[24]" + }, + { + "name": "cnt_sync_in_vio[23]" + }, + { + "name": "cnt_sync_in_vio[22]" + }, + { + "name": "cnt_sync_in_vio[21]" + }, + { + "name": "cnt_sync_in_vio[20]" + }, + { + "name": "cnt_sync_in_vio[19]" + }, + { + "name": "cnt_sync_in_vio[18]" + }, + { + "name": "cnt_sync_in_vio[17]" + }, + { + "name": "cnt_sync_in_vio[16]" + }, + { + "name": "cnt_sync_in_vio[15]" + }, + { + "name": "cnt_sync_in_vio[14]" + }, + { + "name": "cnt_sync_in_vio[13]" + }, + { + "name": "cnt_sync_in_vio[12]" + }, + { + "name": "cnt_sync_in_vio[11]" + }, + { + "name": "cnt_sync_in_vio[10]" + }, + { + "name": "cnt_sync_in_vio[9]" + }, + { + "name": "cnt_sync_in_vio[8]" + }, + { + "name": "cnt_sync_in_vio[7]" + }, + { + "name": "cnt_sync_in_vio[6]" + }, + { + "name": "cnt_sync_in_vio[5]" + }, + { + "name": "cnt_sync_in_vio[4]" + }, + { + "name": "cnt_sync_in_vio[3]" + }, + { + "name": "cnt_sync_in_vio[2]" + }, + { + "name": "cnt_sync_in_vio[1]" + }, + { + "name": "cnt_sync_in_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out20", + "id": 169, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 20, + "nets": [ + { + "name": "cnt_sync_in_high_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_sync_in_high_vio[31]" + }, + { + "name": "cnt_sync_in_high_vio[30]" + }, + { + "name": "cnt_sync_in_high_vio[29]" + }, + { + "name": "cnt_sync_in_high_vio[28]" + }, + { + "name": "cnt_sync_in_high_vio[27]" + }, + { + "name": "cnt_sync_in_high_vio[26]" + }, + { + "name": "cnt_sync_in_high_vio[25]" + }, + { + "name": "cnt_sync_in_high_vio[24]" + }, + { + "name": "cnt_sync_in_high_vio[23]" + }, + { + "name": "cnt_sync_in_high_vio[22]" + }, + { + "name": "cnt_sync_in_high_vio[21]" + }, + { + "name": "cnt_sync_in_high_vio[20]" + }, + { + "name": "cnt_sync_in_high_vio[19]" + }, + { + "name": "cnt_sync_in_high_vio[18]" + }, + { + "name": "cnt_sync_in_high_vio[17]" + }, + { + "name": "cnt_sync_in_high_vio[16]" + }, + { + "name": "cnt_sync_in_high_vio[15]" + }, + { + "name": "cnt_sync_in_high_vio[14]" + }, + { + "name": "cnt_sync_in_high_vio[13]" + }, + { + "name": "cnt_sync_in_high_vio[12]" + }, + { + "name": "cnt_sync_in_high_vio[11]" + }, + { + "name": "cnt_sync_in_high_vio[10]" + }, + { + "name": "cnt_sync_in_high_vio[9]" + }, + { + "name": "cnt_sync_in_high_vio[8]" + }, + { + "name": "cnt_sync_in_high_vio[7]" + }, + { + "name": "cnt_sync_in_high_vio[6]" + }, + { + "name": "cnt_sync_in_high_vio[5]" + }, + { + "name": "cnt_sync_in_high_vio[4]" + }, + { + "name": "cnt_sync_in_high_vio[3]" + }, + { + "name": "cnt_sync_in_high_vio[2]" + }, + { + "name": "cnt_sync_in_high_vio[1]" + }, + { + "name": "cnt_sync_in_high_vio[0]" + } + ] + } + ] } ] } diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit index 516abe72..4d5e12d8 100644 Binary files a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit and b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx index 273aff05..d11cff30 100644 --- a/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx +++ b/projects/duifei/duifei_online_acq_par/project/project.runs/impl_1/system_top.ltx @@ -2086,7 +2086,7 @@ "portIndex": 13, "nets": [ { - "name": "freq_comp_start_1", + "name": "freq_comp_start", "isBus": false } ] @@ -4572,6 +4572,108 @@ ] } ] + }, + { + "name": "probe8", + "id": 110, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 8, + "nets": [ + { + "name": "vio_frequency__0_2", + "isBus": true, + "subnets": [ + { + "name": "vio_frequency__0_2[11]" + }, + { + "name": "vio_frequency__0_2[10]" + }, + { + "name": "vio_frequency__0_2[9]" + }, + { + "name": "vio_frequency__0_2[8]" + }, + { + "name": "vio_frequency__0_2[7]" + }, + { + "name": "vio_frequency__0_2[6]" + }, + { + "name": "vio_frequency__0_2[5]" + }, + { + "name": "vio_frequency__0_2[4]" + }, + { + "name": "vio_frequency__0_2[3]" + }, + { + "name": "vio_frequency__0_2[2]" + }, + { + "name": "vio_frequency__0_2[1]" + }, + { + "name": "vio_frequency__0_2[0]" + } + ] + } + ] + }, + { + "name": "probe9", + "id": 111, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 9, + "portIndex": 9, + "nets": [ + { + "name": "chip_cnt", + "isBus": true, + "subnets": [ + { + "name": "chip_cnt[9]" + }, + { + "name": "chip_cnt[8]" + }, + { + "name": "chip_cnt[7]" + }, + { + "name": "chip_cnt[6]" + }, + { + "name": "chip_cnt[5]" + }, + { + "name": "chip_cnt[4]" + }, + { + "name": "chip_cnt[3]" + }, + { + "name": "chip_cnt[2]" + }, + { + "name": "chip_cnt[1]" + }, + { + "name": "chip_cnt[0]" + } + ] + } + ] } ] }, @@ -4589,7 +4691,7 @@ "pins": [ { "name": "probe0", - "id": 110, + "id": 112, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -4643,7 +4745,7 @@ }, { "name": "probe1", - "id": 111, + "id": 113, "type": "DATA_TRIGGER", "direction": "IN", "isVector": true, @@ -4711,7 +4813,7 @@ "pins": [ { "name": "probe_in0", - "id": 112, + "id": 114, "type": "DATA", "direction": "IN", "isVector": true, @@ -4753,7 +4855,7 @@ }, { "name": "probe_in1", - "id": 113, + "id": 115, "type": "DATA", "direction": "IN", "isVector": true, @@ -4795,7 +4897,7 @@ }, { "name": "probe_in2", - "id": 114, + "id": 116, "type": "DATA", "direction": "IN", "isVector": true, @@ -4837,7 +4939,7 @@ }, { "name": "probe_in3", - "id": 115, + "id": 117, "type": "DATA", "direction": "IN", "isVector": true, @@ -4879,7 +4981,7 @@ }, { "name": "probe_in4", - "id": 116, + "id": 118, "type": "DATA", "direction": "IN", "isVector": true, @@ -4993,7 +5095,7 @@ }, { "name": "probe_in5", - "id": 117, + "id": 119, "type": "DATA", "direction": "IN", "isVector": true, @@ -5313,7 +5415,7 @@ "pins": [ { "name": "probe_out0", - "id": 118, + "id": 120, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5329,7 +5431,7 @@ }, { "name": "probe_out1", - "id": 119, + "id": 121, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5345,7 +5447,7 @@ }, { "name": "probe_out2", - "id": 120, + "id": 122, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5361,7 +5463,7 @@ }, { "name": "probe_out3", - "id": 121, + "id": 123, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5441,7 +5543,7 @@ "pins": [ { "name": "probe_in0", - "id": 122, + "id": 124, "type": "DATA", "direction": "IN", "isVector": false, @@ -5457,7 +5559,7 @@ }, { "name": "probe_in1", - "id": 123, + "id": 125, "type": "DATA", "direction": "IN", "isVector": false, @@ -5487,7 +5589,7 @@ "pins": [ { "name": "probe_in0", - "id": 124, + "id": 126, "type": "DATA", "direction": "IN", "isVector": false, @@ -5503,7 +5605,7 @@ }, { "name": "probe_out0", - "id": 125, + "id": 127, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5512,14 +5614,14 @@ "portIndex": 0, "nets": [ { - "name": "freq_comp_start", + "name": "freq_comp_start_vio", "isBus": false } ] }, { "name": "probe_out1", - "id": 126, + "id": 128, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5561,7 +5663,7 @@ }, { "name": "probe_out2", - "id": 127, + "id": 129, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5577,7 +5679,7 @@ }, { "name": "probe_out3", - "id": 128, + "id": 130, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5688,6 +5790,22 @@ ] } ] + }, + { + "name": "probe_out4", + "id": 131, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 4, + "nets": [ + { + "name": "freq_comp_auto_enable_vio", + "isBus": false + } + ] } ] }, @@ -5705,7 +5823,7 @@ "pins": [ { "name": "probe_out0", - "id": 129, + "id": 132, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5729,7 +5847,7 @@ }, { "name": "probe_out1", - "id": 130, + "id": 133, "type": "DATA", "direction": "OUT", "isVector": false, @@ -5745,7 +5863,7 @@ }, { "name": "probe_out2", - "id": 131, + "id": 134, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5859,7 +5977,7 @@ }, { "name": "probe_out3", - "id": 132, + "id": 135, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5883,7 +6001,7 @@ }, { "name": "probe_out4", - "id": 133, + "id": 136, "type": "DATA", "direction": "OUT", "isVector": true, @@ -5927,7 +6045,7 @@ "pins": [ { "name": "probe_in0", - "id": 134, + "id": 137, "type": "DATA", "direction": "IN", "isVector": true, @@ -5969,7 +6087,7 @@ }, { "name": "probe_in1", - "id": 135, + "id": 138, "type": "DATA", "direction": "IN", "isVector": true, @@ -6011,7 +6129,7 @@ }, { "name": "probe_in2", - "id": 136, + "id": 139, "type": "DATA", "direction": "IN", "isVector": true, @@ -6053,7 +6171,7 @@ }, { "name": "probe_in3", - "id": 137, + "id": 140, "type": "DATA", "direction": "IN", "isVector": true, @@ -6095,7 +6213,7 @@ }, { "name": "probe_in4", - "id": 138, + "id": 141, "type": "DATA", "direction": "IN", "isVector": true, @@ -6125,7 +6243,7 @@ }, { "name": "probe_in5", - "id": 139, + "id": 142, "type": "DATA", "direction": "IN", "isVector": true, @@ -6155,7 +6273,7 @@ }, { "name": "probe_in6", - "id": 140, + "id": 143, "type": "DATA", "direction": "IN", "isVector": true, @@ -6185,7 +6303,7 @@ }, { "name": "probe_in7", - "id": 141, + "id": 144, "type": "DATA", "direction": "IN", "isVector": true, @@ -6215,7 +6333,7 @@ }, { "name": "probe_in8", - "id": 142, + "id": 145, "type": "DATA", "direction": "IN", "isVector": true, @@ -6329,7 +6447,7 @@ }, { "name": "probe_in9", - "id": 143, + "id": 146, "type": "DATA", "direction": "IN", "isVector": true, @@ -6649,7 +6767,7 @@ "pins": [ { "name": "probe_in0", - "id": 144, + "id": 147, "type": "DATA", "direction": "IN", "isVector": true, @@ -6713,9 +6831,25 @@ } ] }, + { + "name": "probe_in1", + "id": 148, + "type": "DATA", + "direction": "IN", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "debug_io_3_IBUF", + "isBus": false + } + ] + }, { "name": "probe_out0", - "id": 145, + "id": 149, "type": "DATA", "direction": "OUT", "isVector": false, @@ -6731,7 +6865,7 @@ }, { "name": "probe_out1", - "id": 146, + "id": 150, "type": "DATA", "direction": "OUT", "isVector": false, @@ -6747,7 +6881,7 @@ }, { "name": "probe_out2", - "id": 147, + "id": 151, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6813,7 +6947,7 @@ }, { "name": "probe_out3", - "id": 148, + "id": 152, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6855,7 +6989,7 @@ }, { "name": "probe_out4", - "id": 149, + "id": 153, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6885,7 +7019,7 @@ }, { "name": "probe_out5", - "id": 150, + "id": 154, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6915,7 +7049,7 @@ }, { "name": "probe_out6", - "id": 151, + "id": 155, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6945,7 +7079,7 @@ }, { "name": "probe_out7", - "id": 152, + "id": 156, "type": "DATA", "direction": "OUT", "isVector": true, @@ -6975,7 +7109,7 @@ }, { "name": "probe_out8", - "id": 153, + "id": 157, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7017,7 +7151,7 @@ }, { "name": "probe_out9", - "id": 154, + "id": 158, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7059,7 +7193,7 @@ }, { "name": "probe_out10", - "id": 155, + "id": 159, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7125,7 +7259,7 @@ }, { "name": "probe_out11", - "id": 156, + "id": 160, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7191,7 +7325,7 @@ }, { "name": "probe_out12", - "id": 157, + "id": 161, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7257,7 +7391,7 @@ }, { "name": "probe_out13", - "id": 158, + "id": 162, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7273,7 +7407,7 @@ }, { "name": "probe_out14", - "id": 159, + "id": 163, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7289,7 +7423,7 @@ }, { "name": "probe_out15", - "id": 160, + "id": 164, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7305,7 +7439,7 @@ }, { "name": "probe_out16", - "id": 161, + "id": 165, "type": "DATA", "direction": "OUT", "isVector": false, @@ -7321,7 +7455,7 @@ }, { "name": "probe_out17", - "id": 162, + "id": 166, "type": "DATA", "direction": "OUT", "isVector": true, @@ -7384,6 +7518,300 @@ ] } ] + }, + { + "name": "probe_out18", + "id": 167, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 15, + "portIndex": 18, + "nets": [ + { + "name": "cnt_switch_to_freq_start_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_switch_to_freq_start_vio[15]" + }, + { + "name": "cnt_switch_to_freq_start_vio[14]" + }, + { + "name": "cnt_switch_to_freq_start_vio[13]" + }, + { + "name": "cnt_switch_to_freq_start_vio[12]" + }, + { + "name": "cnt_switch_to_freq_start_vio[11]" + }, + { + "name": "cnt_switch_to_freq_start_vio[10]" + }, + { + "name": "cnt_switch_to_freq_start_vio[9]" + }, + { + "name": "cnt_switch_to_freq_start_vio[8]" + }, + { + "name": "cnt_switch_to_freq_start_vio[7]" + }, + { + "name": "cnt_switch_to_freq_start_vio[6]" + }, + { + "name": "cnt_switch_to_freq_start_vio[5]" + }, + { + "name": "cnt_switch_to_freq_start_vio[4]" + }, + { + "name": "cnt_switch_to_freq_start_vio[3]" + }, + { + "name": "cnt_switch_to_freq_start_vio[2]" + }, + { + "name": "cnt_switch_to_freq_start_vio[1]" + }, + { + "name": "cnt_switch_to_freq_start_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out19", + "id": 168, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 19, + "nets": [ + { + "name": "cnt_sync_in_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_sync_in_vio[31]" + }, + { + "name": "cnt_sync_in_vio[30]" + }, + { + "name": "cnt_sync_in_vio[29]" + }, + { + "name": "cnt_sync_in_vio[28]" + }, + { + "name": "cnt_sync_in_vio[27]" + }, + { + "name": "cnt_sync_in_vio[26]" + }, + { + "name": "cnt_sync_in_vio[25]" + }, + { + "name": "cnt_sync_in_vio[24]" + }, + { + "name": "cnt_sync_in_vio[23]" + }, + { + "name": "cnt_sync_in_vio[22]" + }, + { + "name": "cnt_sync_in_vio[21]" + }, + { + "name": "cnt_sync_in_vio[20]" + }, + { + "name": "cnt_sync_in_vio[19]" + }, + { + "name": "cnt_sync_in_vio[18]" + }, + { + "name": "cnt_sync_in_vio[17]" + }, + { + "name": "cnt_sync_in_vio[16]" + }, + { + "name": "cnt_sync_in_vio[15]" + }, + { + "name": "cnt_sync_in_vio[14]" + }, + { + "name": "cnt_sync_in_vio[13]" + }, + { + "name": "cnt_sync_in_vio[12]" + }, + { + "name": "cnt_sync_in_vio[11]" + }, + { + "name": "cnt_sync_in_vio[10]" + }, + { + "name": "cnt_sync_in_vio[9]" + }, + { + "name": "cnt_sync_in_vio[8]" + }, + { + "name": "cnt_sync_in_vio[7]" + }, + { + "name": "cnt_sync_in_vio[6]" + }, + { + "name": "cnt_sync_in_vio[5]" + }, + { + "name": "cnt_sync_in_vio[4]" + }, + { + "name": "cnt_sync_in_vio[3]" + }, + { + "name": "cnt_sync_in_vio[2]" + }, + { + "name": "cnt_sync_in_vio[1]" + }, + { + "name": "cnt_sync_in_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out20", + "id": 169, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 20, + "nets": [ + { + "name": "cnt_sync_in_high_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_sync_in_high_vio[31]" + }, + { + "name": "cnt_sync_in_high_vio[30]" + }, + { + "name": "cnt_sync_in_high_vio[29]" + }, + { + "name": "cnt_sync_in_high_vio[28]" + }, + { + "name": "cnt_sync_in_high_vio[27]" + }, + { + "name": "cnt_sync_in_high_vio[26]" + }, + { + "name": "cnt_sync_in_high_vio[25]" + }, + { + "name": "cnt_sync_in_high_vio[24]" + }, + { + "name": "cnt_sync_in_high_vio[23]" + }, + { + "name": "cnt_sync_in_high_vio[22]" + }, + { + "name": "cnt_sync_in_high_vio[21]" + }, + { + "name": "cnt_sync_in_high_vio[20]" + }, + { + "name": "cnt_sync_in_high_vio[19]" + }, + { + "name": "cnt_sync_in_high_vio[18]" + }, + { + "name": "cnt_sync_in_high_vio[17]" + }, + { + "name": "cnt_sync_in_high_vio[16]" + }, + { + "name": "cnt_sync_in_high_vio[15]" + }, + { + "name": "cnt_sync_in_high_vio[14]" + }, + { + "name": "cnt_sync_in_high_vio[13]" + }, + { + "name": "cnt_sync_in_high_vio[12]" + }, + { + "name": "cnt_sync_in_high_vio[11]" + }, + { + "name": "cnt_sync_in_high_vio[10]" + }, + { + "name": "cnt_sync_in_high_vio[9]" + }, + { + "name": "cnt_sync_in_high_vio[8]" + }, + { + "name": "cnt_sync_in_high_vio[7]" + }, + { + "name": "cnt_sync_in_high_vio[6]" + }, + { + "name": "cnt_sync_in_high_vio[5]" + }, + { + "name": "cnt_sync_in_high_vio[4]" + }, + { + "name": "cnt_sync_in_high_vio[3]" + }, + { + "name": "cnt_sync_in_high_vio[2]" + }, + { + "name": "cnt_sync_in_high_vio[1]" + }, + { + "name": "cnt_sync_in_high_vio[0]" + } + ] + } + ] } ] } diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c index 24314f41..1c7c8a1b 100644 --- a/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c +++ b/projects/duifei/duifei_online_acq_par/project/project.sdk/duifei_cmos_48m/src/main.c @@ -384,15 +384,15 @@ int main(void) return FAILURE; } -// // enable single ad9361 tx channels -// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels -// -// // switch ad9361 tx & rx channel -// Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); -// Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); + // enable single ad9361 tx channels + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels + + // switch ad9361 tx & rx channel + Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03); + Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03); // switch to higher frequency - Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_125); + Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125); XGpioPs_WritePin(&Gpio, AD9361_TX_SWITCH, 0); print("Done.\n"); diff --git a/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf index 8304e068..e5acb769 100644 Binary files a/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf and b/projects/duifei/duifei_online_acq_par/project/project.sdk/system_top.hdf differ diff --git a/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v b/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v index dcd1f84f..809cad86 100644 --- a/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v +++ b/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v @@ -21,22 +21,27 @@ module rf_auto_switch_freq( - input clk , - input rst , + input clk , + input rst , // vio control - input start , // rise-edge active, if start, change freq word to the first - input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch - input switch_next_freq , // rise-edge active - input switch_last_freq , // rise-edge active - input [15:0] cnt_valid_to_switch , // clock number from valid to switch + input start , // rise-edge active, if start, change freq word to the first + input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch + input switch_next_freq , // rise-edge active + input switch_last_freq , // rise-edge active + input [15:0] cnt_valid_to_switch , // clock number from valid to switch + input [15:0] cnt_switch_to_freq_start , + input [31:0] cnt_sync_in , + input [31:0] cnt_sync_in_high , // input - input [15:0] freq_hop_words_vio , - input hop_words_valid_vio , - input freq_hop_switch_vio , + input sync_in , // rise-edge or down-edge active + input [15:0] freq_hop_words_vio , + input hop_words_valid_vio , + input freq_hop_switch_vio , // output - output reg [15:0] freq_hop_words_auto = 11'd0 , - output reg hop_words_valid_auto = 1'd0 , - output reg freq_hop_switch_auto = 1'd0 + output reg [15:0] freq_hop_words_auto = 11'd0, + output reg hop_words_valid_auto = 1'd0 , + output reg freq_hop_switch_auto = 1'd0 , + output reg freq_comp_start = 1'b0 // rise-edge or down-edge active ); //************************* rise-edge detect *********************************** @@ -73,6 +78,46 @@ always @ (posedge clk) switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2; switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0]; end +//*********************** sync signal detect *********************************** +reg sync_in_reg = 1'b0; +reg [31:0] sync_in_cnt = 32'd0; +reg sync_in_high_cnt = 32'd0; +reg sync_in_valid = 1'b0; +reg sync_in_valid_d1 = 1'b0; +always @ (posedge clk) + if(rst | start_pulse) begin + sync_in_cnt <= 32'd0; + sync_in_high_cnt <= 32'd0; + end else if(sync_in_cnt == cnt_sync_in) begin + sync_in_cnt <= 32'd0; + sync_in_high_cnt <= 32'd0; + end else if(sync_in == 1'b1) begin + sync_in_cnt <= sync_in_cnt + 1'b1; + sync_in_high_cnt <= sync_in_high_cnt + 1'b1; + end else begin + sync_in_cnt <= sync_in_cnt + 1'b1; + end + + +always @ (posedge clk) + if(rst | start_pulse) + sync_in_reg <= 1'b0; + else if(sync_in_cnt == cnt_sync_in && sync_in_high_cnt > cnt_sync_in_high) + sync_in_reg <= 1'b1; + else if(sync_in_cnt == cnt_sync_in) + sync_in_reg <= 1'b0; + +always @ (posedge clk) + if(rst | start_pulse) + sync_in_valid <= 1'b0; + else if(sync_in_reg != sync_in_valid) + sync_in_valid <= ~sync_in_valid; + +always @ (posedge clk) + if(rst | start_pulse) + sync_in_valid_d1 <= 1'b0; + else + sync_in_valid_d1 <= sync_in_valid; //******************** local freq word control ********************************* reg [15:0] local_freq_word = 16'd0; @@ -89,13 +134,17 @@ rom_freq_word rom_freq_word_inst( always @ (posedge clk) if(rst | start_pulse) - freq_word_cnt <= 8'd0; + freq_word_cnt <= 8'd80; else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0]) freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd80 && sync_in_valid != sync_in_valid_d1) + freq_word_cnt <= 8'd0; else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0]) freq_word_cnt <= 8'd80; else if(switch_next_freq_pulse[0]) freq_word_cnt <= freq_word_cnt + 1'b1; + else if(sync_in_valid != sync_in_valid_d1) + freq_word_cnt <= freq_word_cnt + 1'b1; else if(switch_last_freq_pulse[0]) freq_word_cnt <= freq_word_cnt - 1'b1; else @@ -104,7 +153,7 @@ always @ (posedge clk) always @ (posedge clk) if(rst | start_pulse) local_freq_word_valid <= 1'b0; - else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4]) + else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | sync_in_valid != sync_in_valid_d1) local_freq_word_valid <= 1'b1; else local_freq_word_valid <= 1'b0; @@ -164,4 +213,24 @@ always @ (posedge clk) else freq_hop_switch_auto <= freq_hop_switch_vio; +// freq_comp_start +reg [15:0] freq_comp_start_cnt = 16'd0; +always @ (posedge clk) + if(rst | start_pulse) + freq_comp_start_cnt <= 16'd0; + else if(freq_comp_start_cnt == cnt_switch_to_freq_start) + freq_comp_start_cnt <= 16'd0; + else if(freq_word_valid_cnt == cnt_valid_to_switch) + freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1; + else if(freq_comp_start_cnt != 16'd0) + freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1; + else + freq_comp_start_cnt <= freq_comp_start_cnt; + +always @ (posedge clk) + if(rst | start_pulse) + freq_comp_start <= 1'b0; + else if(freq_comp_start_cnt == cnt_switch_to_freq_start) + freq_comp_start <= ~freq_comp_start; + endmodule diff --git a/projects/duifei/duifei_online_acq_par/rtl/system_top.v b/projects/duifei/duifei_online_acq_par/rtl/system_top.v index 063ed425..ef0d9cf3 100644 --- a/projects/duifei/duifei_online_acq_par/rtl/system_top.v +++ b/projects/duifei/duifei_online_acq_par/rtl/system_top.v @@ -419,30 +419,39 @@ wire rf_ctrl_mode_vio ; wire switch_next_freq_vio; wire switch_last_freq_vio; wire [15:0] cnt_valid_to_switch_vio; +wire [15:0] cnt_switch_to_freq_start_vio; +wire [31:0] cnt_sync_in_vio; +wire [31:0] cnt_sync_in_high_vio; (*dont_touch = "true"*) wire vio_switch; (*dont_touch = "true"*) wire vio_switch_auto; (*dont_touch = "true"*) wire [15:0] vio_frequency; (*dont_touch = "true"*) wire [15:0] vio_frequency_auto; wire hop_words_valid_auto; +wire freq_comp_start_auto ; rf_auto_switch_freq u_rf_auto_switch_freq( - .clk (clk_48m ), - .rst (sys_rst ), + .clk (clk_48m ), + .rst (sys_rst ), // vio control - .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first - .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch - .switch_next_freq (switch_next_freq_vio ), // rise-edge active - .switch_last_freq (switch_last_freq_vio ), // rise-edge active - .cnt_valid_to_switch (cnt_valid_to_switch_vio ), + .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first + .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch + .switch_next_freq (switch_next_freq_vio ), // rise-edge active + .switch_last_freq (switch_last_freq_vio ), // rise-edge active + .cnt_valid_to_switch (cnt_valid_to_switch_vio ), + .cnt_switch_to_freq_start (cnt_switch_to_freq_start_vio ), + .cnt_sync_in (cnt_sync_in_vio[31:0] ), + .cnt_sync_in_high (cnt_sync_in_high_vio[31:0] ), // input - .freq_hop_words_vio (vio_frequency[15:0] ), - .hop_words_valid_vio (1'b0 ), - .freq_hop_switch_vio (vio_switch ), + .sync_in (debug_io_3 ), + .freq_hop_words_vio (vio_frequency[15:0] ), + .hop_words_valid_vio (1'b0 ), + .freq_hop_switch_vio (vio_switch ), // output - .freq_hop_words_auto (vio_frequency_auto[15:0] ), - .hop_words_valid_auto (hop_words_valid_auto ), - .freq_hop_switch_auto (vio_switch_auto ) + .freq_hop_words_auto (vio_frequency_auto[15:0] ), + .hop_words_valid_auto (hop_words_valid_auto ), + .freq_hop_switch_auto (vio_switch_auto ), + .freq_comp_start (freq_comp_start_auto ) ); ant_rf_ctrl u_ant_rf_ctrl @@ -664,6 +673,8 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal // <----------------------- insert receiver logic below -----------------------> // <---------------------------------------------------------------------------> wire freq_comp_start ; +wire freq_comp_auto_enable_vio; +wire freq_comp_start_vio; wire freq_comp_busy ; wire [7:0] dmf_num_per_ch ; wire [31:0] freq_manual ; @@ -689,6 +700,8 @@ wire [17:0] ch4_peak_value_i ; wire [17:0] ch4_peak_value_q ; wire [ 9:0] ch4_peak_index ; +assign freq_comp_start = (freq_comp_auto_enable_vio == 1'b1) ? freq_comp_start_auto : freq_comp_start_vio; + freq_comp #( .FREQ_WORD_LOWER (-4194304 ), .FREQ_WORD_UPPER (4194303 ), @@ -747,7 +760,16 @@ freq_comp #( .ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index ); +reg [9:0] chip_cnt = 'b0; +always @(posedge sys_clk) begin + if (sys_rst) begin + chip_cnt <= 'b0; + end + else begin + chip_cnt <= chip_cnt + 1'b1; + end +end //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// ILAs and VIOs ///////////////////////////////// @@ -780,7 +802,11 @@ vio_rfcontrl u_vio_rfcontrl .probe_out15(switch_next_freq_vio ), // output wire [0 : 0] probe_out15 .probe_out16(switch_last_freq_vio ), // output wire [0 : 0] probe_out16 .probe_out17(cnt_valid_to_switch_vio[15:0] ), // output wire [15: 0] probe_out17 - .probe_in0 (vio_frequency_auto[15:0] ) // input wire [10: 0] probe_in0 + .probe_out18(cnt_switch_to_freq_start_vio[15:0] ), // output wire [15: 0] probe_out18 + .probe_out19(cnt_sync_in_vio[31:0] ), // output wire [31: 0] probe_out19 + .probe_out20(cnt_sync_in_high_vio[31:0] ), // output wire [31: 0] probe_out20 + .probe_in0 (vio_frequency_auto[15:0] ), // input wire [15: 0] probe_in0 + .probe_in1 (debug_io_3 ) // input wire [0: 0] probe_in1 ); vio_ant_test u_vio_ant_test @@ -896,17 +922,19 @@ ila_2x12x1024 u_ila_tx .probe1 (tx_ch1_q ) // input wire [11:0] probe1 ); -ila_8x12x8192 u_ila_rx +ila_rx_data_cnt u_ila_rx ( - .clk (sys_clk ), // input wire clk - .probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0 - .probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1 - .probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2 - .probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3 - .probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4 - .probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5 - .probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6 - .probe7 (rx_cal_ch4_q ) // input wire [11:0] probe7 + .clk (sys_clk ), // input wire clk + .probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0 + .probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1 + .probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2 + .probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3 + .probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4 + .probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5 + .probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6 + .probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7 + .probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8 + .probe9 (chip_cnt ) // input wire [9:0] probe9 ); ila_cal u_ila_cal @@ -941,12 +969,13 @@ vio_manual_ctrl u_vio_manual_ctrl vio_freq_comp u_vio_freq_comp ( - .clk (sys_clk ), // input wire clk - .probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0 - .probe_out0 (freq_comp_start ), // output wire [0 : 0] probe_out0 - .probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1 - .probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2 - .probe_out3 (freq_manual ) // output wire [31 : 0] probe_out3 + .clk (sys_clk ), // input wire clk + .probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0 + .probe_out0 (freq_comp_start_vio ), // output wire [0 : 0] probe_out0 + .probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1 + .probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2 + .probe_out3 (freq_manual ), // output wire [31 : 0] probe_out3 + .probe_out4 (freq_comp_auto_enable_vio ) // output wire [0 : 0] probe_out4 ); ila_freq_comp u_ila_freq_comp